2018-08-13 00:29:12 +08:00
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2019-02-18 14:16:29 +08:00
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#include <util.h>
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#include <acrn_common.h>
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2021-04-23 15:50:57 +08:00
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#include <asm/guest/vcpu.h>
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#include <asm/mmu.h>
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#include <asm/guest/trusty.h>
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2021-10-25 18:44:36 +08:00
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#include <asm/vtd.h>
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2018-08-13 00:29:12 +08:00
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2018-11-06 23:43:47 +08:00
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#define CAT__(A,B) A ## B
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#define CAT_(A,B) CAT__(A,B)
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2018-08-13 00:29:12 +08:00
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#define CTASSERT(expr) \
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2018-12-08 00:30:49 +08:00
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typedef int32_t CAT_(CTA_DummyType,__LINE__)[(expr) ? 1 : -1]
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2018-08-13 00:29:12 +08:00
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2019-04-19 02:20:54 +08:00
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/* This is to make sure the 16 bits vpid won't overflow */
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2019-12-09 14:08:53 +08:00
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#if ((CONFIG_MAX_VM_NUM * MAX_VCPUS_PER_VM) > 0xffffU)
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2019-04-19 02:20:54 +08:00
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#error "VM number or VCPU number are too big"
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#endif
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2020-02-27 07:51:16 +08:00
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#if ((CONFIG_HV_RAM_START & (MEM_2M - 1UL)) != 0UL)
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#error "CONFIG_HV_RAM_START must be aligned to 2MB"
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#endif
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2021-10-25 18:44:36 +08:00
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#if ((MAX_IR_ENTRIES < 256U) || (MAX_IR_ENTRIES > 0x10000U) || (MAX_IR_ENTRIES & (MAX_IR_ENTRIES -1)) != 0U)
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#error "MAX_IR_ENTRIES must in the region of [256,0x10000] and be 2^n"
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2020-05-09 16:23:37 +08:00
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#endif
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2018-08-13 00:29:12 +08:00
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/* Build time sanity checks to make sure hard-coded offset
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* is matching the actual offset!
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*/
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2018-09-28 10:44:33 +08:00
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CTASSERT(CPU_CONTEXT_OFFSET_RAX == offsetof(struct acrn_gp_regs, rax));
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CTASSERT(CPU_CONTEXT_OFFSET_RBX == offsetof(struct acrn_gp_regs, rbx));
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CTASSERT(CPU_CONTEXT_OFFSET_RCX == offsetof(struct acrn_gp_regs, rcx));
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CTASSERT(CPU_CONTEXT_OFFSET_RDX == offsetof(struct acrn_gp_regs, rdx));
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CTASSERT(CPU_CONTEXT_OFFSET_RBP == offsetof(struct acrn_gp_regs, rbp));
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CTASSERT(CPU_CONTEXT_OFFSET_RSI == offsetof(struct acrn_gp_regs, rsi));
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CTASSERT(CPU_CONTEXT_OFFSET_RDI == offsetof(struct acrn_gp_regs, rdi));
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CTASSERT(CPU_CONTEXT_OFFSET_R8 == offsetof(struct acrn_gp_regs, r8));
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CTASSERT(CPU_CONTEXT_OFFSET_R9 == offsetof(struct acrn_gp_regs, r9));
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CTASSERT(CPU_CONTEXT_OFFSET_R10 == offsetof(struct acrn_gp_regs, r10));
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CTASSERT(CPU_CONTEXT_OFFSET_R11 == offsetof(struct acrn_gp_regs, r11));
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CTASSERT(CPU_CONTEXT_OFFSET_R12 == offsetof(struct acrn_gp_regs, r12));
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CTASSERT(CPU_CONTEXT_OFFSET_R13 == offsetof(struct acrn_gp_regs, r13));
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CTASSERT(CPU_CONTEXT_OFFSET_R14 == offsetof(struct acrn_gp_regs, r14));
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CTASSERT(CPU_CONTEXT_OFFSET_R15 == offsetof(struct acrn_gp_regs, r15));
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2018-08-13 00:29:12 +08:00
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CTASSERT(CPU_CONTEXT_OFFSET_CR2 == offsetof(struct run_context, cr2));
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CTASSERT(CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL
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== offsetof(struct run_context, ia32_spec_ctrl));
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CTASSERT(CPU_CONTEXT_OFFSET_RFLAGS == offsetof(struct run_context, rflags));
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CTASSERT(CPU_CONTEXT_OFFSET_CR3 - CPU_CONTEXT_OFFSET_EXTCTX_START
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== offsetof(struct ext_context, cr3));
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CTASSERT(CPU_CONTEXT_OFFSET_IDTR - CPU_CONTEXT_OFFSET_EXTCTX_START
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== offsetof(struct ext_context, idtr));
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CTASSERT(CPU_CONTEXT_OFFSET_LDTR - CPU_CONTEXT_OFFSET_EXTCTX_START
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== offsetof(struct ext_context, ldtr));
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CTASSERT((sizeof(struct trusty_startup_param)
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+ sizeof(struct trusty_key_info)) < 0x1000U);
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CTASSERT(NR_WORLD == 2);
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2021-07-07 15:38:07 +08:00
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CTASSERT(sizeof(struct acrn_io_request) == (4096U/ACRN_IO_REQUEST_MAX));
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