hv: vtd: add two paramters for dmar_assign_irte
idx_in: - If the caller of dmar_assign_irte passes a valid IRTE index, it will be resued; - If the caller of dmar_assign_irte passes INVALID_IRTE_ID as IRTE index, the function will allocate a new IRTE. idx_out: This paramter return the actual index of IRTE used. The caller need to check whether the return value is valid or not. Also this patch adds an internal function alloc_irte. The function takes count as input paramter to allocate continuous IRTEs. The count can only be 1, 2, 4, 8, 16 or 32. This is prepared for multiple MSI vector support. Tracked-On: #4831 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Binbin Wu
wenlingz
parent
9c52b353fa
commit
2fe4280cfa
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@ -126,23 +126,23 @@ static void ptirq_build_physical_msi(struct acrn_vm *vm,
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intr_src.is_msi = true;
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intr_src.pid_paddr = pid_paddr;
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intr_src.src.msi.value = entry->phys_sid.msi_id.bdf;
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ret = dmar_assign_irte(&intr_src, &irte, (uint16_t)entry->allocated_pirq);
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ret = dmar_assign_irte(&intr_src, &irte, (uint16_t)entry->allocated_pirq, &ir_index.index);
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if (ret == 0) {
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/*
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* Update the MSI interrupt source to point to the IRTE
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* SHV is set to 0 as ACRN disables MMC (Multi-Message Capable
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* for MSI devices.
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*/
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entry->pmsi.data.full = 0U;
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ir_index.index = (uint16_t)entry->allocated_pirq;
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entry->pmsi.addr.full = 0UL;
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entry->pmsi.addr.ir_bits.intr_index_high = ir_index.bits.index_high;
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entry->pmsi.addr.ir_bits.shv = 0U;
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entry->pmsi.addr.ir_bits.intr_format = 0x1U;
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entry->pmsi.addr.ir_bits.intr_index_low = ir_index.bits.index_low;
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entry->pmsi.addr.ir_bits.constant = 0xFEEU;
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if (ir_index.index != INVALID_IRTE_ID) {
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/*
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* Update the MSI interrupt source to point to the IRTE
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* SHV is set to 0 as ACRN disables MMC (Multi-Message Capable
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* for MSI devices.
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*/
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entry->pmsi.addr.ir_bits.intr_index_high = ir_index.bits.index_high;
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entry->pmsi.addr.ir_bits.shv = 0U;
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entry->pmsi.addr.ir_bits.intr_format = 0x1U;
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entry->pmsi.addr.ir_bits.intr_index_low = ir_index.bits.index_low;
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entry->pmsi.addr.ir_bits.constant = 0xFEEU;
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}
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} else {
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/* In case there is no corresponding IOMMU, for example, if the
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* IOMMU is ignored, pass the MSI info in Compatibility Format
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@ -223,15 +223,18 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
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intr_src.is_msi = false;
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intr_src.pid_paddr = 0UL;
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intr_src.src.ioapic_id = ioapic_irq_to_ioapic_id(phys_irq);
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ret = dmar_assign_irte(&intr_src, &irte, (uint16_t)phys_irq);
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ret = dmar_assign_irte(&intr_src, &irte, (uint16_t)phys_irq, &ir_index.index);
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if (ret == 0) {
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ir_index.index = (uint16_t)phys_irq;
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rte.ir_bits.vector = vector;
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rte.ir_bits.constant = 0U;
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rte.ir_bits.intr_index_high = ir_index.bits.index_high;
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rte.ir_bits.intr_format = 1U;
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rte.ir_bits.intr_index_low = ir_index.bits.index_low;
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if (ir_index.index != INVALID_IRTE_ID) {
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rte.ir_bits.vector = vector;
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rte.ir_bits.constant = 0U;
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rte.ir_bits.intr_index_high = ir_index.bits.index_high;
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rte.ir_bits.intr_format = 1U;
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rte.ir_bits.intr_index_low = ir_index.bits.index_low;
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} else {
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rte.bits.intr_mask = 1;
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}
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} else {
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rte.bits.dest_mode = IOAPIC_RTE_DESTMODE_LOGICAL;
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rte.bits.delivery_mode = delmode;
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@ -128,6 +128,7 @@ struct dmar_drhd_rt {
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uint64_t root_table_addr;
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uint64_t ir_table_addr;
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uint64_t irte_alloc_bitmap[CONFIG_MAX_IR_ENTRIES/64U];
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uint64_t qi_queue;
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uint16_t qi_tail;
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@ -1261,7 +1262,30 @@ int32_t init_iommu(void)
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return ret;
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}
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int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry *irte, uint16_t index)
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/* Allocate continuous IRTEs specified by num, num can be 1, 2, 4, 8, 16, 32 */
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static uint16_t alloc_irtes(struct dmar_drhd_rt *dmar_unit, const uint16_t num)
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{
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uint16_t irte_idx;
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uint64_t mask = (1UL << num) - 1U;
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uint64_t test_mask;
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ASSERT((bitmap_weight(num) == 1U) && (num <= 32U));
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spinlock_obtain(&dmar_unit->lock);
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for (irte_idx = 0U; irte_idx < CONFIG_MAX_IR_ENTRIES; irte_idx += num) {
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test_mask = mask << (irte_idx & 0x3FU);
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if ((dmar_unit->irte_alloc_bitmap[irte_idx >> 6U] & test_mask) == 0UL) {
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dmar_unit->irte_alloc_bitmap[irte_idx >> 6U] |= test_mask;
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break;
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}
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}
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spinlock_release(&dmar_unit->lock);
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return (irte_idx < CONFIG_MAX_IR_ENTRIES) ? irte_idx: INVALID_IRTE_ID;
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}
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int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry *irte,
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uint16_t idx_in, uint16_t *idx_out)
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{
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struct dmar_drhd_rt *dmar_unit;
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union dmar_ir_entry *ir_table, *ir_entry;
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@ -1279,42 +1303,49 @@ int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry
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}
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if (is_dmar_unit_valid(dmar_unit, sid)) {
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ret = 0;
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dmar_enable_intr_remapping(dmar_unit);
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ir_table = (union dmar_ir_entry *)hpa2hva(dmar_unit->ir_table_addr);
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ir_entry = ir_table + index;
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if (intr_src->pid_paddr != 0UL) {
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union dmar_ir_entry irte_pi;
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/* irte is in remapped mode format, convert to posted mode format */
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irte_pi.value.lo_64 = 0UL;
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irte_pi.value.hi_64 = 0UL;
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irte_pi.bits.post.vector = irte->bits.remap.vector;
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irte_pi.bits.post.svt = 0x1UL;
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irte_pi.bits.post.sid = sid.value;
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irte_pi.bits.post.present = 0x1UL;
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irte_pi.bits.post.mode = 0x1UL;
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irte_pi.bits.post.pda_l = (intr_src->pid_paddr) >> 6U;
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irte_pi.bits.post.pda_h = (intr_src->pid_paddr) >> 32U;
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*ir_entry = irte_pi;
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} else {
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/* Fields that have not been initialized explicitly default to 0 */
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irte->bits.remap.svt = 0x1UL;
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irte->bits.remap.sid = sid.value;
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irte->bits.remap.present = 0x1UL;
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irte->bits.remap.trigger_mode = trigger_mode;
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*ir_entry = *irte;
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*idx_out = idx_in;
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if (idx_in == INVALID_IRTE_ID) {
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*idx_out = alloc_irtes(dmar_unit, 1U);
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}
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iommu_flush_cache(ir_entry, sizeof(union dmar_ir_entry));
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dmar_invalid_iec(dmar_unit, index, 0U, false);
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if (*idx_out < CONFIG_MAX_IR_ENTRIES) {
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ir_entry = ir_table + *idx_out;
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if (intr_src->pid_paddr != 0UL) {
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union dmar_ir_entry irte_pi;
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/* irte is in remapped mode format, convert to posted mode format */
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irte_pi.value.lo_64 = 0UL;
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irte_pi.value.hi_64 = 0UL;
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irte_pi.bits.post.vector = irte->bits.remap.vector;
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irte_pi.bits.post.svt = 0x1UL;
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irte_pi.bits.post.sid = sid.value;
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irte_pi.bits.post.present = 0x1UL;
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irte_pi.bits.post.mode = 0x1UL;
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irte_pi.bits.post.pda_l = (intr_src->pid_paddr) >> 6U;
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irte_pi.bits.post.pda_h = (intr_src->pid_paddr) >> 32U;
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*ir_entry = irte_pi;
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} else {
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/* Fields that have not been initialized explicitly default to 0 */
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irte->bits.remap.svt = 0x1UL;
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irte->bits.remap.sid = sid.value;
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irte->bits.remap.present = 0x1UL;
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irte->bits.remap.trigger_mode = trigger_mode;
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*ir_entry = *irte;
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}
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iommu_flush_cache(ir_entry, sizeof(union dmar_ir_entry));
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dmar_invalid_iec(dmar_unit, *idx_out, 0U, false);
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}
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ret = 0;
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}
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return ret;
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}
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@ -1338,4 +1369,5 @@ void dmar_free_irte(const struct intr_source *intr_src, uint16_t index)
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iommu_flush_cache(ir_entry, sizeof(union dmar_ir_entry));
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dmar_invalid_iec(dmar_unit, index, 0U, false);
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}
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}
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@ -11,6 +11,7 @@
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#include <platform_acpi_info.h>
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#define INVALID_DRHD_INDEX 0xFFFFFFFFU
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#define INVALID_IRTE_ID 0xFFFFU
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/*
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* Intel IOMMU register specification per version 1.0 public spec.
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@ -675,13 +676,15 @@ int32_t init_iommu(void);
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*
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* @param[in] intr_src filled with type of interrupt source and the source
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* @param[in] irte filled with info about interrupt deliverymode, destination and destination mode
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* @param[in] index into Interrupt Remapping Table
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* @param[in] idx_in if this value is INVALID_IRTE_ID, a new IRTE will be allocated, otherwise, use the IRTE directly.
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* @param[out] idx_out return the actual IRTE index used, need to check whether the returned value is valid or not.
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*
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* @retval -EINVAL if corresponding DMAR is not present
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* @retval 0 otherwise
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* @retval -EINVAL if corresponding DMAR is not preset
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* @retval 0 on success, caller should check whether the returned start index is valid or not.
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*
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*/
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int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry *irte, uint16_t index);
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int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry *irte,
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uint16_t idx_in, uint16_t *idx_out);
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/**
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* @brief Free RTE for Interrupt Remapping Table.
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@ -29,6 +29,10 @@ typedef int32_t CAT_(CTA_DummyType,__LINE__)[(expr) ? 1 : -1]
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#error "CONFIG_HV_RAM_SIZE must be integral multiple of 2MB"
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#endif
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#if ((CONFIG_MAX_IR_ENTRIES < 256U) || (CONFIG_MAX_IR_ENTRIES & (CONFIG_MAX_IR_ENTRIES -1)) != 0U)
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#error "CONFIG_MAX_IR_ENTRIES must >=256 and be 2^n"
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#endif
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/* Build time sanity checks to make sure hard-coded offset
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* is matching the actual offset!
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*/
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