158 lines
3.9 KiB
C
158 lines
3.9 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT snps_designware_intc
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/* This implementation supports only the regular irqs
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* No support for priority filtering
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* No support for vectored interrupts
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* Firqs are also not supported
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* This implementation works only when sw_isr_table is enabled in zephyr
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*/
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#include <device.h>
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#include <irq_nextlevel.h>
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#include "intc_dw.h"
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#include <soc.h>
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static ALWAYS_INLINE void dw_ictl_dispatch_child_isrs(uint32_t intr_status,
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uint32_t isr_base_offset)
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{
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uint32_t intr_bitpos, intr_offset;
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/* Dispatch lower level ISRs depending upon the bit set */
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while (intr_status) {
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intr_bitpos = find_lsb_set(intr_status) - 1;
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intr_status &= ~(1 << intr_bitpos);
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intr_offset = isr_base_offset + intr_bitpos;
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_sw_isr_table[intr_offset].isr(
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_sw_isr_table[intr_offset].arg);
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}
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}
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static int dw_ictl_initialize(const struct device *dev)
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{
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const struct dw_ictl_config *config = dev->config;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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/* disable all interrupts */
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regs->irq_inten_l = 0U;
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regs->irq_inten_h = 0U;
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return 0;
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}
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static void dw_ictl_isr(const struct device *dev)
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{
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const struct dw_ictl_config *config = dev->config;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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dw_ictl_dispatch_child_isrs(regs->irq_maskstatus_l,
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config->isr_table_offset);
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if (config->numirqs > 32) {
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dw_ictl_dispatch_child_isrs(regs->irq_maskstatus_h,
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config->isr_table_offset + 32);
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}
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}
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static inline void dw_ictl_intr_enable(const struct device *dev,
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unsigned int irq)
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{
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const struct dw_ictl_config *config = dev->config;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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if (irq < 32) {
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regs->irq_inten_l |= (1 << irq);
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} else {
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regs->irq_inten_h |= (1 << (irq - 32));
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}
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}
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static inline void dw_ictl_intr_disable(const struct device *dev,
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unsigned int irq)
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{
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const struct dw_ictl_config *config = dev->config;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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if (irq < 32) {
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regs->irq_inten_l &= ~(1 << irq);
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} else {
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regs->irq_inten_h &= ~(1 << (irq - 32));
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}
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}
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static inline unsigned int dw_ictl_intr_get_state(const struct device *dev)
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{
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const struct dw_ictl_config *config = dev->config;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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if (regs->irq_inten_l) {
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return 1;
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}
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if (config->numirqs > 32) {
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if (regs->irq_inten_h) {
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return 1;
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}
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}
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return 0;
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}
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static int dw_ictl_intr_get_line_state(const struct device *dev,
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unsigned int irq)
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{
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const struct dw_ictl_config *config = dev->config;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)config->base_addr;
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if (config->numirqs > 32) {
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if ((regs->irq_inten_h & BIT(irq - 32)) != 0) {
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return 1;
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}
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} else {
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if ((regs->irq_inten_l & BIT(irq)) != 0) {
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return 1;
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}
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}
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return 0;
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}
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static void dw_ictl_config_irq(const struct device *dev);
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static const struct dw_ictl_config dw_config = {
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.base_addr = DT_INST_REG_ADDR(0),
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.numirqs = DT_INST_PROP(0, num_irqs),
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.isr_table_offset = CONFIG_DW_ISR_TBL_OFFSET,
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.config_func = dw_ictl_config_irq,
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};
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static const struct irq_next_level_api dw_ictl_apis = {
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.intr_enable = dw_ictl_intr_enable,
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.intr_disable = dw_ictl_intr_disable,
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.intr_get_state = dw_ictl_intr_get_state,
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.intr_get_line_state = dw_ictl_intr_get_line_state,
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};
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DEVICE_DT_INST_DEFINE(0, dw_ictl_initialize, NULL,
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NULL, &dw_config, PRE_KERNEL_1,
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CONFIG_DW_ICTL_INIT_PRIORITY, &dw_ictl_apis);
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static void dw_ictl_config_irq(const struct device *port)
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{
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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dw_ictl_isr,
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DEVICE_DT_INST_GET(0),
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DT_INST_IRQ(0, sense));
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}
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