111 lines
3.3 KiB
C
111 lines
3.3 KiB
C
/*
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* Copyright (c) 2020 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _I2S_LITEI2S__H
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#define _I2S_LITEI2S__H
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#include <device.h>
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#include <drivers/i2s.h>
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#include <devicetree.h>
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/* i2s register offsets*/
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#define I2S_EV_STATUS_REG_OFFSET 0x0
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#define I2S_EV_PENDING_REG_OFFSET 0x4
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#define I2S_EV_ENABLE_REG_OFFSET 0x8
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#define I2S_CONTROL_REG_OFFSET 0xc
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#define I2S_STATUS_REG_OFFSET 0x10
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#define I2S_CONFIG_REG_OFFSET 0x20
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/* i2s configuration mask*/
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#define I2S_CONF_FORMAT_OFFSET 0
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#define I2S_CONF_SAMPLE_WIDTH_OFFSET 2
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#define I2S_CONF_LRCK_FREQ_OFFSET 8
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#define I2S_CONF_FORMAT_MASK (0x3 << I2S_CONF_FORMAT_OFFSET)
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#define I2S_CONF_SAMPLE_WIDTH_MASK (0x3f << I2S_CONF_SAMPLE_WIDTH_OFFSET)
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#define I2S_CONF_LRCK_MASK (0xffffff << I2S_CONF_LRCK_FREQ_OFFSET)
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/* i2s control register options*/
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#define I2S_ENABLE (1 << 0)
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#define I2S_FIFO_RESET (1 << 1)
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/* i2s event*/
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#define I2S_EV_ENABLE (1 << 0)
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/* i2s event types*/
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#define I2S_EV_READY (1 << 0)
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#define I2S_EV_ERROR (1 << 1)
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/* i2s rx*/
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#define I2S_RX_BASE_ADDR DT_REG_ADDR_BY_NAME(DT_NODELABEL(i2s_rx), control)
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#define I2S_RX_EV_STATUS_REG (I2S_RX_BASE_ADDR + I2S_EV_STATUS_REG_OFFSET)
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#define I2S_RX_EV_PENDING_REG (I2S_RX_BASE_ADDR + I2S_EV_PENDING_REG_OFFSET)
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#define I2S_RX_EV_ENABLE_REG (I2S_RX_BASE_ADDR + I2S_EV_ENABLE_REG_OFFSET)
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#define I2S_RX_CONTROL_REG (I2S_RX_BASE_ADDR + I2S_CONTROL_REG_OFFSET)
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#define I2S_RX_STATUS_REG (I2S_RX_BASE_ADDR + I2S_STATUS_REG_OFFSET)
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#define I2S_RX_CONFIG_REG (I2S_RX_BASE_ADDR + I2S_CONFIG_REG_OFFSET)
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#define I2S_RX_STAT_CHANNEL_CONCATENATED_OFFSET 31
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#define I2S_RX_STAT_CHANNEL_CONCATENATED_MASK \
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(0x1 << I2S_RX_STAT_CHANNEL_CONCATENATED_OFFSET)
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#define I2S_RX_FIFO_ADDR DT_REG_ADDR_BY_NAME(DT_NODELABEL(i2s_rx), fifo)
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#define I2S_RX_FIFO_DEPTH DT_PROP(DT_NODELABEL(i2s_rx), fifo_depth)
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/* i2s tx*/
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#define I2S_TX_BASE_ADDR DT_REG_ADDR_BY_NAME(DT_NODELABEL(i2s_tx), control)
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#define I2S_TX_EV_STATUS_REG (I2S_RX_BASE_ADDR + I2S_EV_STATUS_REG_OFFSET)
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#define I2S_TX_EV_PENDING_REG (I2S_TX_BASE_ADDR + I2S_EV_PENDING_REG_OFFSET)
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#define I2S_TX_EV_ENABLE_REG (I2S_TX_BASE_ADDR + I2S_EV_ENABLE_REG_OFFSET)
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#define I2S_TX_CONTROL_REG (I2S_TX_BASE_ADDR + I2S_CONTROL_REG_OFFSET)
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#define I2S_TX_STATUS_REG (I2S_TX_BASE_ADDR + I2S_STATUS_REG_OFFSET)
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#define I2S_TX_CONFIG_REG (I2S_TX_BASE_ADDR + I2S_CONFIG_REG_OFFSET)
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#define I2S_TX_STAT_CHANNEL_CONCATENATED_OFFSET 24
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#define I2S_TX_STAT_CHANNEL_CONCATENATED_MASK \
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(0x1 << I2S_TX_STAT_CHANNEL_CONCATENATED_OFFSET)
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#define I2S_TX_FIFO_ADDR DT_REG_ADDR_BY_NAME(DT_NODELABEL(i2s_tx), fifo)
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#define I2S_TX_FIFO_DEPTH DT_PROP(DT_NODELABEL(i2s_tx), fifo_depth)
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enum litex_i2s_fmt {
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LITEX_I2S_STANDARD = 1,
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LITEX_I2S_LEFT_JUSTIFIED = 2,
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};
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struct queue_item {
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void *mem_block;
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size_t size;
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};
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/* Minimal ring buffer implementation */
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struct ring_buf {
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struct queue_item *buf;
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uint16_t len;
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uint16_t head;
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uint16_t tail;
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};
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struct stream {
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int32_t state;
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struct k_sem sem;
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struct i2s_config cfg;
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struct ring_buf mem_block_queue;
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void *mem_block;
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};
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/* Device run time data */
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struct i2s_litex_data {
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struct stream rx;
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struct stream tx;
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};
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/* Device const configuration */
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struct i2s_litex_cfg {
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uint32_t base;
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uint32_t fifo_base;
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uint16_t fifo_depth;
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void (*irq_config)(const struct device *dev);
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};
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#endif /* _I2S_LITEI2S__H */
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