144 lines
4.5 KiB
C
144 lines
4.5 KiB
C
/*
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* Copyright (c) 2019 Interay Solutions B.V.
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* Copyright (c) 2019 Oane Kingma
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_GECKO_PRIV_H_
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#define ZEPHYR_DRIVERS_ETHERNET_ETH_GECKO_PRIV_H_
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#include <kernel.h>
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#include <zephyr/types.h>
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#define ETH_GECKO_MTU NET_ETH_MTU
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#define SILABS_OUI_B0 0x00
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#define SILABS_OUI_B1 0x0B
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#define SILABS_OUI_B2 0x57
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#define ETH_TX_BUF_SIZE 1536
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#define ETH_TX_BUF_COUNT 2
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#define ETH_RX_BUF_SIZE 128
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#define ETH_RX_BUF_COUNT 32
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#define ETH_BUF_ALIGNMENT 16
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#define ETH_DESC_ALIGNMENT 4
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#define ETH_TX_USED BIT(31)
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#define ETH_TX_WRAP BIT(30)
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#define ETH_TX_ERROR BIT(29)
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#define ETH_TX_UNDERRUN BIT(28)
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#define ETH_TX_EXHAUSTED BIT(27)
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#define ETH_TX_NO_CRC BIT(16)
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#define ETH_TX_LAST BIT(15)
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#define ETH_TX_LENGTH (2048-1)
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#define ETH_RX_ADDRESS ~(ETH_DESC_ALIGNMENT-1)
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#define ETH_RX_WRAP BIT(1)
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#define ETH_RX_OWNERSHIP BIT(0)
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#define ETH_RX_BROADCAST BIT(31)
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#define ETH_RX_MULTICAST_HASH BIT(30)
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#define ETH_RX_UNICAST_HASH BIT(29)
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#define ETH_RX_EXT_ADDR BIT(28)
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#define ETH_RX_SAR1 BIT(26)
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#define ETH_RX_SAR2 BIT(25)
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#define ETH_RX_SAR3 BIT(24)
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#define ETH_RX_SAR4 BIT(23)
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#define ETH_RX_TYPE_ID BIT(22)
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#define ETH_RX_VLAN_TAG BIT(21)
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#define ETH_RX_PRIORITY_TAG BIT(20)
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#define ETH_RX_VLAN_PRIORITY (0x7UL<<17)
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#define ETH_RX_CFI BIT(16)
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#define ETH_RX_EOF BIT(15)
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#define ETH_RX_SOF BIT(14)
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#define ETH_RX_OFFSET (0x3UL<<12)
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#define ETH_RX_LENGTH (4096-1)
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#define ETH_RX_ENABLE(base) (base->NETWORKCTRL |= ETH_NETWORKCTRL_ENBRX)
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#define ETH_RX_DISABLE(base) (base->NETWORKCTRL &= ~ETH_NETWORKCTRL_ENBRX)
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#define ETH_TX_ENABLE(base) (base->NETWORKCTRL |= ETH_NETWORKCTRL_ENBTX)
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#define ETH_TX_DISABLE(base) (base->NETWORKCTRL &= ~ETH_NETWORKCTRL_ENBTX)
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struct eth_buf_desc {
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uint32_t address;
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uint32_t status;
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};
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struct eth_gecko_pin_list {
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struct soc_gpio_pin mdio[2];
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struct soc_gpio_pin rmii[7];
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};
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/* Device constant configuration parameters */
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struct eth_gecko_dev_cfg {
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ETH_TypeDef *regs;
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const struct eth_gecko_pin_list *pin_list;
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uint32_t pin_list_size;
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void (*config_func)(void);
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struct phy_gecko_dev phy;
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};
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/* Device run time data */
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struct eth_gecko_dev_data {
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struct net_if *iface;
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uint8_t mac_addr[6];
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struct k_sem tx_sem;
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struct k_sem rx_sem;
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K_KERNEL_STACK_MEMBER(rx_thread_stack,
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CONFIG_ETH_GECKO_RX_THREAD_STACK_SIZE);
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struct k_thread rx_thread;
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bool link_up;
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};
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#define DEV_NAME(dev) ((dev)->name)
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#define DEV_CFG(dev) \
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((const struct eth_gecko_dev_cfg *)(dev)->config)
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#define DEV_DATA(dev) \
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((struct eth_gecko_dev_data *)(dev)->data)
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/* PHY Management pins */
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#define PIN_PHY_MDC {DT_INST_PROP_BY_IDX(0, location_phy_mdc, 1), \
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DT_INST_PROP_BY_IDX(0, location_phy_mdc, 2), gpioModePushPull,\
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0}
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#define PIN_PHY_MDIO {DT_INST_PROP_BY_IDX(0, location_phy_mdio, 1), \
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DT_INST_PROP_BY_IDX(0, location_phy_mdio, 2), gpioModePushPull,\
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0}
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#define PIN_LIST_PHY {PIN_PHY_MDC, PIN_PHY_MDIO}
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/* RMII pins excluding reference clock, handled by board.c */
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#define PIN_RMII_CRSDV {DT_INST_PROP_BY_IDX(0, location_rmii_crs_dv, 1),\
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DT_INST_PROP_BY_IDX(0, location_rmii_crs_dv, 2), gpioModeInput, 0}
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#define PIN_RMII_TXD0 {DT_INST_PROP_BY_IDX(0, location_rmii_txd0, 1),\
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DT_INST_PROP_BY_IDX(0, location_rmii_txd0, 2), gpioModePushPull, 0}
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#define PIN_RMII_TXD1 {DT_INST_PROP_BY_IDX(0, location_rmii_txd1, 1),\
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DT_INST_PROP_BY_IDX(0, location_rmii_txd1, 2), gpioModePushPull, 0}
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#define PIN_RMII_TX_EN {DT_INST_PROP_BY_IDX(0, location_rmii_tx_en, 1),\
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DT_INST_PROP_BY_IDX(0, location_rmii_tx_en, 2), gpioModePushPull, 0}
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#define PIN_RMII_RXD0 {DT_INST_PROP_BY_IDX(0, location_rmii_rxd0, 1),\
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DT_INST_PROP_BY_IDX(0, location_rmii_rxd0, 2), gpioModeInput, 0}
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#define PIN_RMII_RXD1 {DT_INST_PROP_BY_IDX(0, location_rmii_rxd1, 1),\
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DT_INST_PROP_BY_IDX(0, location_rmii_rxd1, 2), gpioModeInput, 0}
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#define PIN_RMII_RX_ER {DT_INST_PROP_BY_IDX(0, location_rmii_rx_er, 1),\
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DT_INST_PROP_BY_IDX(0, location_rmii_rx_er, 2), gpioModeInput, 0}
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#define PIN_LIST_RMII {PIN_RMII_CRSDV, PIN_RMII_TXD0, PIN_RMII_TXD1, \
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PIN_RMII_TX_EN, PIN_RMII_RXD0, PIN_RMII_RXD1, PIN_RMII_RX_ER}
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/* RMII reference clock is not included in RMII pin set
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* #define PIN_RMII_REFCLK {DT_INST_PROP_BY_IDX(0, location_rmii_refclk, 1),\
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* DT_INST_PROP_BY_IDX(0, location_rmii_refclk, 2), gpioModePushPull, 0}
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*/
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#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_GECKO_PRIV_H_ */
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