211 lines
12 KiB
C
Executable File
211 lines
12 KiB
C
Executable File
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __RDC_DEFS_IMX6SX__
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#define __RDC_DEFS_IMX6SX__
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/*!
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* @addtogroup rdc_def_imx6sx
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief RDC master assignment. */
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enum _rdc_mda
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{
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rdcMdaA9L2Cache = 0U, /*!< A9 L2 Cache RDC Master. */
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rdcMdaM4 = 1U, /*!< M4 RDC Master. */
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rdcMdaGpu = 2U, /*!< GPU RDC Master. */
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rdcMdaCsi1 = 3U, /*!< Csi1 RDC Master. */
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rdcMdaCsi2 = 4U, /*!< Csi2 RDC Master. */
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rdcMdaLcdif1 = 5U, /*!< Lcdif1 RDC Master. */
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rdcMdaLcdif2 = 6U, /*!< Lcdif2 RDC Master. */
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rdcMdaPxp = 7U, /*!< Pxp RDC Master. */
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rdcMdaPcieCtrl = 8U, /*!< Pcie Ctrl RDC Master. */
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rdcMdaDap = 9U, /*!< Dap RDC Master. */
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rdcMdaCaam = 10U, /*!< Caam RDC Master. */
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rdcMdaSdmaPeriph = 11U, /*!< Sdma Periph RDC Master. */
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rdcMdaSdmaBurst = 12U, /*!< Sdma Burst RDC Master. */
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rdcMdaApbhdma = 13U, /*!< Apbhdma RDC Master. */
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rdcMdaRawnand = 14U, /*!< Rawnand RDC Master. */
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rdcMdaUsdhc1 = 15U, /*!< Usdhc1 RDC Master. */
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rdcMdaUsdhc2 = 16U, /*!< Usdhc2 RDC Master. */
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rdcMdaUsdhc3 = 17U, /*!< Usdhc3 RDC Master. */
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rdcMdaUsdhc4 = 18U, /*!< Usdhc4 RDC Master. */
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rdcMdaUsb = 19U, /*!< USB RDC Master. */
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rdcMdaMlb = 20U, /*!< MLB RDC Master. */
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rdcMdaTestPort = 21U, /*!< Test Port RDC Master. */
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rdcMdaEnet1Tx = 22U, /*!< Enet1 Tx RDC Master. */
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rdcMdaEnet1Rx = 23U, /*!< Enet1 Rx Master. */
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rdcMdaEnet2Tx = 24U, /*!< Enet2 Tx RDC Master. */
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rdcMdaEnet2Rx = 25U, /*!< Enet2 Rx RDC Master. */
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rdcMdaSdmaPort = 26U, /*!< Sdma Port RDC Master. */
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};
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/*! @brief RDC peripheral assignment. */
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enum _rdc_pdap
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{
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rdcPdapPwm1 = 0U, /*!< Pwm1 RDC Peripheral. */
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rdcPdapPwm2 = 1U, /*!< Pwm2 RDC Peripheral. */
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rdcPdapPwm3 = 2U, /*!< Pwm3 RDC Peripheral. */
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rdcPdapPwm4 = 3U, /*!< Pwm4 RDC Peripheral. */
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rdcPdapCan1 = 4U, /*!< Can1 RDC Peripheral. */
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rdcPdapCan2 = 5U, /*!< Can2 RDC Peripheral. */
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rdcPdapGpt = 6U, /*!< Gpt RDC Peripheral. */
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rdcPdapGpio1 = 7U, /*!< Gpio1 RDC Peripheral. */
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rdcPdapGpio2 = 8U, /*!< Gpio2 RDC Peripheral. */
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rdcPdapGpio3 = 9U, /*!< Gpio3 RDC Peripheral. */
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rdcPdapGpio4 = 10U, /*!< Gpio4 RDC Peripheral. */
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rdcPdapGpio5 = 11U, /*!< Gpio5 RDC Peripheral. */
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rdcPdapGpio6 = 12U, /*!< Gpio6 RDC Peripheral. */
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rdcPdapGpio7 = 13U, /*!< Gpio7 RDC Peripheral. */
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rdcPdapKpp = 14U, /*!< Kpp RDC Peripheral. */
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rdcPdapWdog1 = 15U, /*!< Wdog1 RDC Peripheral. */
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rdcPdapWdog2 = 16U, /*!< Wdog2 RDC Peripheral. */
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rdcPdapCcm = 17U, /*!< Ccm RDC Peripheral. */
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rdcPdapAnatopDig = 18U, /*!< AnatopDig RDC Peripheral. */
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rdcPdapSnvsHp = 19U, /*!< SnvsHp RDC Peripheral. */
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rdcPdapEpit1 = 20U, /*!< Epit1 RDC Peripheral. */
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rdcPdapEpit2 = 21U, /*!< Epit2 RDC Peripheral. */
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rdcPdapSrc = 22U, /*!< Src RDC Peripheral. */
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rdcPdapGpc = 23U, /*!< Gpc RDC Peripheral. */
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rdcPdapIomuxc = 24U, /*!< Iomuxc RDC Peripheral. */
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rdcPdapIomuxcGpr = 25U, /*!< IomuxcGpr RDC Peripheral. */
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rdcPdapCanfdCan1 = 26U, /*!< Canfd Can1 RDC Peripheral. */
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rdcPdapSdma = 27U, /*!< Sdma RDC Peripheral. */
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rdcPdapCanfdCan2 = 28U, /*!< Canfd Can2 RDC Peripheral. */
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rdcPdapRdcSema421 = 29U, /*!< Rdc Sema421 RDC Peripheral. */
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rdcPdapRdcSema422 = 30U, /*!< Rdc Sema422 RDC Peripheral. */
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rdcPdapRdc = 31U, /*!< Rdc RDC Peripheral. */
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rdcPdapAipsTz1GlobalEnable1 = 32U, /*!< AipsTz1GlobalEnable1 RDC Peripheral. */
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rdcPdapAipsTz1GlobalEnable2 = 33U, /*!< AipsTz1GlobalEnable2 RDC Peripheral. */
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rdcPdapUsb02hPl301 = 34U, /*!< Usb02hPl301 RDC Peripheral. */
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rdcPdapUsb02hUsb = 35U, /*!< Usb02hUsb RDC Peripheral. */
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rdcPdapEnet1 = 36U, /*!< Enet1 RDC Peripheral. */
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rdcPdapMlb2550 = 37U, /*!< Mlb2550 RDC Peripheral. */
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rdcPdapUsdhc1 = 38U, /*!< Usdhc1 RDC Peripheral. */
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rdcPdapUsdhc2 = 39U, /*!< Usdhc2 RDC Peripheral. */
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rdcPdapUsdhc3 = 40U, /*!< Usdhc3 RDC Peripheral. */
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rdcPdapUsdhc4 = 41U, /*!< Usdhc4 RDC Peripheral. */
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rdcPdapI2c1 = 42U, /*!< I2c1 RDC Peripheral. */
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rdcPdapI2c2 = 43U, /*!< I2c2 RDC Peripheral. */
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rdcPdapI2c3 = 44U, /*!< I2c3 RDC Peripheral. */
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rdcPdapRomcp = 45U, /*!< Romcp RDC Peripheral. */
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rdcPdapMmdc = 46U, /*!< Mmdc RDC Peripheral. */
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rdcPdapEnet2 = 47U, /*!< Enet2 RDC Peripheral. */
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rdcPdapEim = 48U, /*!< Eim RDC Peripheral. */
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rdcPdapOcotpCtrlWrapper = 49U, /*!< OcotpCtrlWrapper RDC Peripheral. */
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rdcPdapCsu = 50U, /*!< Csu RDC Peripheral. */
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rdcPdapPerfmon1 = 51U, /*!< Perfmon1 RDC Peripheral. */
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rdcPdapPerfmon2 = 52U, /*!< Perfmon2 RDC Peripheral. */
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rdcPdapAxiMon = 53U, /*!< AxiMon RDC Peripheral. */
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rdcPdapTzasc1 = 54U, /*!< Tzasc1 RDC Peripheral. */
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rdcPdapSai1 = 55U, /*!< Sai1 RDC Peripheral. */
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rdcPdapAudmux = 56U, /*!< Audmux RDC Peripheral. */
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rdcPdapSai2 = 57U, /*!< Sai2 RDC Peripheral. */
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rdcPdapQspi1 = 58U, /*!< Qspi1 RDC Peripheral. */
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rdcPdapQspi2 = 59U, /*!< Qspi2 RDC Peripheral. */
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rdcPdapUart2 = 60U, /*!< Uart2 RDC Peripheral. */
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rdcPdapUart3 = 61U, /*!< Uart3 RDC Peripheral. */
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rdcPdapUart4 = 62U, /*!< Uart4 RDC Peripheral. */
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rdcPdapUart5 = 63U, /*!< Uart5 RDC Peripheral. */
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rdcPdapI2c4 = 64U, /*!< I2c4 RDC Peripheral. */
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rdcPdapQosc = 65U, /*!< Qosc RDC Peripheral. */
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rdcPdapCaam = 66U, /*!< Caam RDC Peripheral. */
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rdcPdapDap = 67U, /*!< Dap RDC Peripheral. */
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rdcPdapAdc1 = 68U, /*!< Adc1 RDC Peripheral. */
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rdcPdapAdc2 = 69U, /*!< Adc2 RDC Peripheral. */
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rdcPdapWdog3 = 70U, /*!< Wdog3 RDC Peripheral. */
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rdcPdapEcspi5 = 71U, /*!< Ecspi5 RDC Peripheral. */
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rdcPdapSema4 = 72U, /*!< Sema4 RDC Peripheral. */
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rdcPdapMuA = 73U, /*!< MuA RDC Peripheral. */
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rdcPdapCanfdCpu = 74U, /*!< Canfd Cpu RDC Peripheral. */
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rdcPdapMuB = 75U, /*!< MuB RDC Peripheral. */
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rdcPdapUart6 = 76U, /*!< Uart6 RDC Peripheral. */
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rdcPdapPwm5 = 77U, /*!< Pwm5 RDC Peripheral. */
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rdcPdapPwm6 = 78U, /*!< Pwm6 RDC Peripheral. */
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rdcPdapPwm7 = 79U, /*!< Pwm7 RDC Peripheral. */
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rdcPdapPwm8 = 80U, /*!< Pwm8 RDC Peripheral. */
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rdcPdapAipsTz3GlobalEnable0 = 81U, /*!< AipsTz3GlobalEnable0 RDC Peripheral. */
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rdcPdapAipsTz3GlobalEnable1 = 82U, /*!< AipsTz3GlobalEnable1 RDC Peripheral. */
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rdcPdapSpdif = 84U, /*!< Spdif RDC Peripheral. */
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rdcPdapEcspi1 = 85U, /*!< Ecspi1 RDC Peripheral. */
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rdcPdapEcspi2 = 86U, /*!< Ecspi2 RDC Peripheral. */
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rdcPdapEcspi3 = 87U, /*!< Ecspi3 RDC Peripheral. */
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rdcPdapEcspi4 = 88U, /*!< Ecspi4 RDC Peripheral. */
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rdcPdapUart1 = 91U, /*!< Uart1 RDC Peripheral. */
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rdcPdapEsai = 92U, /*!< Esai RDC Peripheral. */
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rdcPdapSsi1 = 93U, /*!< Ssi1 RDC Peripheral. */
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rdcPdapSsi2 = 94U, /*!< Ssi2 RDC Peripheral. */
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rdcPdapSsi3 = 95U, /*!< Ssi3 RDC Peripheral. */
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rdcPdapAsrc = 96U, /*!< Asrc RDC Peripheral. */
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rdcPdapSpbaMaMegamix = 98U, /*!< SpbaMaMegamix RDC Peripheral. */
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rdcPdapGis = 99U, /*!< Gis RDC Peripheral. */
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rdcPdapDcic1 = 100U, /*!< Dcic1 RDC Peripheral. */
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rdcPdapDcic2 = 101U, /*!< Dcic2 RDC Peripheral. */
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rdcPdapCsi1 = 102U, /*!< Csi1 RDC Peripheral. */
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rdcPdapPxp = 103U, /*!< Pxp RDC Peripheral. */
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rdcPdapCsi2 = 104U, /*!< Csi2 RDC Peripheral. */
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rdcPdapLcdif1 = 105U, /*!< Lcdif1 RDC Peripheral. */
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rdcPdapLcdif2 = 106U, /*!< Lcdif2 RDC Peripheral. */
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rdcPdapVadc = 107U, /*!< Vadc RDC Peripheral. */
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rdcPdapVdec = 108U, /*!< Vdec RDC Peripheral. */
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rdcPdapSpDisplaymix = 109U, /*!< SpDisplaymix RDC Peripheral. */
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};
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/*! @brief RDC memory region */
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enum _rdc_mr
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{
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rdcMrMmdc = 0U, /*!< alignment 4096 */
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rdcMrMmdcLast = 7U, /*!< alignment 4096 */
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rdcMrQspi1 = 8U, /*!< alignment 4096 */
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rdcMrQspi1Last = 15U, /*!< alignment 4096 */
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rdcMrQspi2 = 16U, /*!< alignment 4096 */
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rdcMrQspi2Last = 23U, /*!< alignment 4096 */
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rdcMrWeim = 24U, /*!< alignment 4096 */
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rdcMrWeimLast = 31U, /*!< alignment 4096 */
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rdcMrPcie = 32U, /*!< alignment 4096 */
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rdcMrPcieLast = 39U, /*!< alignment 4096 */
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rdcMrOcram = 40U, /*!< alignment 128 */
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rdcMrOcramLast = 44U, /*!< alignment 128 */
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rdcMrOcramS = 45U, /*!< alignment 128 */
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rdcMrOcramSLast = 49U, /*!< alignment 128 */
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rdcMrOcramL2 = 50U, /*!< alignment 128 */
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rdcMrOcramL2Last = 54U, /*!< alignment 128 */
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};
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#endif /* __RDC_DEFS_IMX6SX__ */
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/*******************************************************************************
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* EOF
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******************************************************************************/
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