388 lines
9.2 KiB
C
388 lines
9.2 KiB
C
/*
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* Copyright (c) 2018 Justin Watson
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <gpio.h>
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#include "gpio_utils.h"
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typedef void (*config_func_t)(struct device *dev);
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struct gpio_sam_config {
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Pio *regs;
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config_func_t config_func;
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u32_t periph_id;
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};
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struct gpio_sam_runtime {
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sys_slist_t cb;
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};
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#define DEV_CFG(dev) \
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((const struct gpio_sam_config *const)(dev)->config->config_info)
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static int gpio_sam_config(struct device *dev, int access_op, u32_t pin,
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int flags)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Pio *const pio = cfg->regs;
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u32_t mask = 1 << pin;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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/* Setup the pin direcion. */
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
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pio->PIO_OER = mask;
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} else {
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pio->PIO_ODR = mask;
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}
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/* Setup interrupt configuration. */
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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return -ENOTSUP;
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}
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/* Enable the interrupt. */
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pio->PIO_IER = mask;
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/* Enable the additional interrupt modes. */
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pio->PIO_AIMER = mask;
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if (flags & GPIO_INT_EDGE) {
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pio->PIO_ESR = mask;
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} else {
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pio->PIO_LSR = mask;
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}
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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/* Set to high-level or rising edge. */
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pio->PIO_REHLSR = mask;
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} else {
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/* Set to low-level or falling edge. */
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pio->PIO_FELLSR = mask;
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}
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} else {
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/* Disable the interrupt. */
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pio->PIO_IDR = mask;
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/* Disable ther additional interrupt modes. */
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pio->PIO_AIMDR = mask;
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}
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/* Setup Pull-up resistor. */
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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/* Enable pull-up. */
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pio->PIO_PUER = mask;
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} else {
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pio->PIO_PUDR = mask;
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}
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/* Setup Pull-down resistor. */
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
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pio->PIO_PPDER = mask;
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} else {
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pio->PIO_PPDDR = mask;
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}
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#if defined(SOC_SERIES_SAM3X)
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/* Setup debounce. */
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if (flags & GPIO_INT_DEBOUNCE) {
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pio->PIO_DIFSR = mask;
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} else {
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pio->PIO_SCIFSR = mask;
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}
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#elif defined(SOC_SERIES_SAM4S) || defined(SOC_SERIES_SAME70)
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/* Setup debounce. */
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if (flags & GPIO_INT_DEBOUNCE) {
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pio->PIO_IFSCER = mask;
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} else {
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pio->PIO_IFSCDR = mask;
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}
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#endif
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/* Enable the PIO to control the pin (instead of a peripheral). */
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pio->PIO_PER = mask;
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return 0;
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}
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static int gpio_sam_write(struct device *dev, int access_op, u32_t pin,
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u32_t value)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Pio *const pio = cfg->regs;
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u32_t mask = 1 << pin;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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if (value) {
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/* Set the pin. */
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pio->PIO_SODR = mask;
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} else {
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/* Clear the pin. */
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pio->PIO_CODR = mask;
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}
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break;
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case GPIO_ACCESS_BY_PORT:
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if (value) {
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/* Set all pins. */
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pio->PIO_SODR = 0xffffffff;
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} else {
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/* Clear all pins. */
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pio->PIO_CODR = 0xffffffff;
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_sam_read(struct device *dev, int access_op, u32_t pin,
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u32_t *value)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Pio *const pio = cfg->regs;
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*value = pio->PIO_PDSR;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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*value = (*value >> pin) & 1;
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break;
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case GPIO_ACCESS_BY_PORT:
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static void gpio_sam_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Pio *const pio = cfg->regs;
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struct gpio_sam_runtime *context = dev->driver_data;
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u32_t int_stat;
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int_stat = pio->PIO_ISR;
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_gpio_fire_callbacks(&context->cb, dev, int_stat);
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}
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static int gpio_sam_manage_callback(struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_sam_runtime *context = port->driver_data;
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_gpio_manage_callback(&context->cb, callback, set);
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return 0;
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}
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static int gpio_sam_enable_callback(struct device *port,
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int access_op, u32_t pin)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(port);
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Pio *const pio = cfg->regs;
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u32_t mask;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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mask = BIT(pin);
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break;
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case GPIO_ACCESS_BY_PORT:
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mask = 0xFFFFFFFF;
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break;
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default:
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return -ENOTSUP;
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}
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pio->PIO_IER |= mask;
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return 0;
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}
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static int gpio_sam_disable_callback(struct device *port,
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int access_op, u32_t pin)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(port);
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Pio *const pio = cfg->regs;
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u32_t mask;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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mask = BIT(pin);
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break;
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case GPIO_ACCESS_BY_PORT:
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mask = 0xFFFFFFFF;
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break;
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default:
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return -ENOTSUP;
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}
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pio->PIO_IDR |= mask;
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return 0;
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}
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static const struct gpio_driver_api gpio_sam_api = {
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.config = gpio_sam_config,
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.write = gpio_sam_write,
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.read = gpio_sam_read,
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.manage_callback = gpio_sam_manage_callback,
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.enable_callback = gpio_sam_enable_callback,
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.disable_callback = gpio_sam_disable_callback,
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};
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int gpio_sam_init(struct device *dev)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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/* The peripheral clock must be enabled for the interrupts to work. */
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soc_pmc_peripheral_enable(cfg->periph_id);
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cfg->config_func(dev);
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return 0;
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}
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/* PORT A */
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#ifdef CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS
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static void port_a_sam_config_func(struct device *dev);
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static const struct gpio_sam_config port_a_sam_config = {
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.regs = (Pio *)CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS,
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.periph_id = CONFIG_GPIO_SAM_PORTA_PERIPHERAL_ID,
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.config_func = port_a_sam_config_func,
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};
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static struct gpio_sam_runtime port_a_sam_runtime;
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DEVICE_AND_API_INIT(port_a_sam, CONFIG_GPIO_SAM_PORTA_LABEL, gpio_sam_init,
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&port_a_sam_runtime, &port_a_sam_config, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
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static void port_a_sam_config_func(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_GPIO_SAM_PORTA_IRQ, CONFIG_GPIO_SAM_PORTA_IRQ_PRIO,
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gpio_sam_isr, DEVICE_GET(port_a_sam), 0);
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irq_enable(CONFIG_GPIO_SAM_PORTA_IRQ);
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}
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#endif /* CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS */
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/* PORT B */
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#ifdef CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS
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static void port_b_sam_config_func(struct device *dev);
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static const struct gpio_sam_config port_b_sam_config = {
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.regs = (Pio *)CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS,
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.periph_id = CONFIG_GPIO_SAM_PORTB_PERIPHERAL_ID,
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.config_func = port_b_sam_config_func,
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};
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static struct gpio_sam_runtime port_b_sam_runtime;
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DEVICE_AND_API_INIT(port_b_sam, CONFIG_GPIO_SAM_PORTB_LABEL, gpio_sam_init,
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&port_b_sam_runtime, &port_b_sam_config, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
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static void port_b_sam_config_func(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_GPIO_SAM_PORTB_IRQ, CONFIG_GPIO_SAM_PORTB_IRQ_PRIO,
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gpio_sam_isr, DEVICE_GET(port_b_sam), 0);
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irq_enable(CONFIG_GPIO_SAM_PORTB_IRQ);
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}
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#endif /* CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS */
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/* PORT C */
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#ifdef CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS
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static void port_c_sam_config_func(struct device *dev);
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static const struct gpio_sam_config port_c_sam_config = {
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.regs = (Pio *)CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS,
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.periph_id = CONFIG_GPIO_SAM_PORTC_PERIPHERAL_ID,
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.config_func = port_c_sam_config_func,
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};
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static struct gpio_sam_runtime port_c_sam_runtime;
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DEVICE_AND_API_INIT(port_c_sam, CONFIG_GPIO_SAM_PORTC_LABEL, gpio_sam_init,
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&port_c_sam_runtime, &port_c_sam_config, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
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static void port_c_sam_config_func(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_GPIO_SAM_PORTC_IRQ, CONFIG_GPIO_SAM_PORTC_IRQ_PRIO,
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gpio_sam_isr, DEVICE_GET(port_c_sam), 0);
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irq_enable(CONFIG_GPIO_SAM_PORTC_IRQ);
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}
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#endif /* CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS */
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/* PORT D */
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#ifdef CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS
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static void port_d_sam_config_func(struct device *dev);
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static const struct gpio_sam_config port_d_sam_config = {
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.regs = (Pio *)CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS,
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.periph_id = CONFIG_GPIO_SAM_PORTD_PERIPHERAL_ID,
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.config_func = port_d_sam_config_func,
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};
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static struct gpio_sam_runtime port_d_sam_runtime;
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DEVICE_AND_API_INIT(port_d_sam, CONFIG_GPIO_SAM_PORTD_LABEL, gpio_sam_init,
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&port_d_sam_runtime, &port_d_sam_config, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
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static void port_d_sam_config_func(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_GPIO_SAM_PORTD_IRQ, CONFIG_GPIO_SAM_PORTD_IRQ_PRIO,
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gpio_sam_isr, DEVICE_GET(port_d_sam), 0);
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irq_enable(CONFIG_GPIO_SAM_PORTD_IRQ);
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}
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#endif /* CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS */
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/* PORT E */
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#ifdef CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS
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static void port_e_sam_config_func(struct device *dev);
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static const struct gpio_sam_config port_e_sam_config = {
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.regs = (Pio *)CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS,
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.periph_id = CONFIG_GPIO_SAM_PORTE_PERIPHERAL_ID,
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.config_func = port_e_sam_config_func,
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};
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static struct gpio_sam_runtime port_e_sam_runtime;
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DEVICE_AND_API_INIT(port_e_sam, CONFIG_GPIO_SAM_PORTE_LABEL, gpio_sam_init,
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&port_e_sam_runtime, &port_e_sam_config, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
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static void port_e_sam_config_func(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_GPIO_SAM_PORTE_IRQ, CONFIG_GPIO_SAM_PORTE_IRQ_PRIO,
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gpio_sam_isr, DEVICE_GET(port_e_sam), 0);
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irq_enable(CONFIG_GPIO_SAM_PORTE_IRQ);
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}
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#endif /* CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS */
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