227 lines
6.6 KiB
C
227 lines
6.6 KiB
C
/*
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* Copyright (c) 2020 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_pwm
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#include <assert.h>
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#include <drivers/pwm.h>
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#include <dt-bindings/clock/npcx_clock.h>
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#include <drivers/clock_control.h>
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#include <kernel.h>
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#include <soc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_npcx, LOG_LEVEL_ERR);
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/* 16-bit period cycles/prescaler in NPCX PWM modules */
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#define NPCX_PWM_MAX_PRESCALER (1UL << (16))
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#define NPCX_PWM_MAX_PERIOD_CYCLES (1UL << (16))
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/* PWM clock sources */
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#define NPCX_PWM_CLOCK_APB2_LFCLK 0
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#define NPCX_PWM_CLOCK_FX 1
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#define NPCX_PWM_CLOCK_FR 2
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#define NPCX_PWM_CLOCK_RESERVED 3
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/* PWM heart-beat mode selection */
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#define NPCX_PWM_HBM_NORMAL 0
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#define NPCX_PWM_HBM_25 1
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#define NPCX_PWM_HBM_50 2
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#define NPCX_PWM_HBM_100 3
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/* Device config */
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struct pwm_npcx_config {
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/* pwm controller base address */
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uintptr_t base;
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/* clock configuration */
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struct npcx_clk_cfg clk_cfg;
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/* Output buffer - open drain */
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const bool is_od;
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/* pinmux configuration */
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const uint8_t alts_size;
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const struct npcx_alt *alts_list;
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};
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/* Driver data */
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struct pwm_npcx_data {
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/* PWM cycles per second */
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uint32_t cycles_per_sec;
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};
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/* Driver convenience defines */
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#define DRV_CONFIG(dev) ((const struct pwm_npcx_config *)(dev)->config)
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#define DRV_DATA(dev) ((struct pwm_npcx_data *)(dev)->data)
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#define HAL_INSTANCE(dev) (struct pwm_reg *)(DRV_CONFIG(dev)->base)
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/* PWM local functions */
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static void pwm_npcx_configure(const struct device *dev, int clk_bus)
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{
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const struct pwm_npcx_config *const config = DRV_CONFIG(dev);
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struct pwm_reg *const inst = HAL_INSTANCE(dev);
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/* Disable PWM for module configuration first */
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inst->PWMCTL &= ~BIT(NPCX_PWMCTL_PWR);
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/* Set default PWM polarity to normal */
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inst->PWMCTL &= ~BIT(NPCX_PWMCTL_INVP);
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/* Turn off PWM heart-beat mode */
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SET_FIELD(inst->PWMCTL, NPCX_PWMCTL_HB_DC_CTL_FIELD,
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NPCX_PWM_HBM_NORMAL);
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/* Select APB CLK/LFCLK clock sources to PWM module by default */
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SET_FIELD(inst->PWMCTLEX, NPCX_PWMCTLEX_FCK_SEL_FIELD,
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NPCX_PWM_CLOCK_APB2_LFCLK);
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/* Select clock source to LFCLK by flag, otherwise APB clock source */
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if (clk_bus == NPCX_CLOCK_BUS_LFCLK)
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inst->PWMCTL |= BIT(NPCX_PWMCTL_CKSEL);
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else
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inst->PWMCTL &= ~BIT(NPCX_PWMCTL_CKSEL);
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/* Select output buffer type of io pad */
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if (config->is_od)
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inst->PWMCTLEX |= BIT(NPCX_PWMCTLEX_OD_OUT);
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else
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inst->PWMCTLEX &= ~BIT(NPCX_PWMCTLEX_OD_OUT);
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}
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/* PWM api functions */
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static int pwm_npcx_pin_set(const struct device *dev, uint32_t pwm,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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/* Single channel for each pwm device */
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ARG_UNUSED(pwm);
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struct pwm_npcx_data *const data = DRV_DATA(dev);
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struct pwm_reg *const inst = HAL_INSTANCE(dev);
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int prescaler;
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if (pulse_cycles > period_cycles)
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return -EINVAL;
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/* Disable PWM before configuring */
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inst->PWMCTL &= ~BIT(NPCX_PWMCTL_PWR);
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/* Select PWM inverted polarity (ie. active-low pulse). */
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if (flags & PWM_POLARITY_INVERTED)
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inst->PWMCTL |= BIT(NPCX_PWMCTL_INVP);
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else
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inst->PWMCTL &= ~BIT(NPCX_PWMCTL_INVP);
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/* If pulse_cycles is 0, return directly since PWM is already off */
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if (pulse_cycles == 0)
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return 0;
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/*
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* Calculate PWM prescaler that let period_cycles map to
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* maximum pwm period cycles and won't exceed it.
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* Then prescaler = ceil (period_cycles / pwm_max_period_cycles)
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*/
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prescaler = ceiling_fraction(period_cycles, NPCX_PWM_MAX_PERIOD_CYCLES);
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if (prescaler > NPCX_PWM_MAX_PRESCALER)
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return -EINVAL;
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/* Set PWM prescaler.*/
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inst->PRSC = prescaler - 1;
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/* Set PWM period cycles */
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inst->CTR = (period_cycles / prescaler) - 1;
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/* Set PWM pulse cycles */
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inst->DCR = (pulse_cycles / prescaler) - 1;
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LOG_DBG("freq %d, pre %d, period %d, pulse %d",
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data->cycles_per_sec / period_cycles,
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inst->PRSC + 1, inst->CTR + 1, inst->DCR + 1);
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/* Enable PWM now */
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inst->PWMCTL |= BIT(NPCX_PWMCTL_PWR);
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return 0;
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}
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static int pwm_npcx_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
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uint64_t *cycles)
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{
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/* Single channel for each pwm device */
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ARG_UNUSED(pwm);
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struct pwm_npcx_data *const data = DRV_DATA(dev);
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*cycles = data->cycles_per_sec;
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return 0;
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}
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/* PWM driver registration */
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static const struct pwm_driver_api pwm_npcx_driver_api = {
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.pin_set = pwm_npcx_pin_set,
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.get_cycles_per_sec = pwm_npcx_get_cycles_per_sec
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};
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static int pwm_npcx_init(const struct device *dev)
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{
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const struct pwm_npcx_config *const config = DRV_CONFIG(dev);
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struct pwm_npcx_data *const data = DRV_DATA(dev);
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struct pwm_reg *const inst = HAL_INSTANCE(dev);
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const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
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int ret;
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/*
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* NPCX PWM modulee mixes byte and word registers together. Make sure
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* word reg access via structure won't break into two byte reg accesses
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* unexpectedly by toolchains options or attributes. If so, stall here.
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*/
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NPCX_REG_WORD_ACCESS_CHECK(inst->PRSC, 0xA55A);
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/* Turn on device clock first and get source clock freq. */
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ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
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&config->clk_cfg);
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if (ret < 0) {
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LOG_ERR("Turn on PWM clock fail %d", ret);
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return ret;
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}
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ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
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&config->clk_cfg, &data->cycles_per_sec);
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if (ret < 0) {
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LOG_ERR("Get PWM clock rate error %d", ret);
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return ret;
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}
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/* Configure PWM device initially */
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pwm_npcx_configure(dev, config->clk_cfg.bus);
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/* Configure pin-mux for PWM device */
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npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 1);
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return 0;
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}
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#define NPCX_PWM_INIT(inst) \
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static const struct npcx_alt pwm_alts##inst[] = \
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NPCX_DT_ALT_ITEMS_LIST(inst); \
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\
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static const struct pwm_npcx_config pwm_npcx_cfg_##inst = { \
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.base = DT_INST_REG_ADDR(inst), \
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.clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst), \
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.is_od = DT_INST_PROP(inst, drive_open_drain), \
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.alts_size = ARRAY_SIZE(pwm_alts##inst), \
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.alts_list = pwm_alts##inst, \
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}; \
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\
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static struct pwm_npcx_data pwm_npcx_data_##inst; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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&pwm_npcx_init, NULL, \
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&pwm_npcx_data_##inst, &pwm_npcx_cfg_##inst, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&pwm_npcx_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(NPCX_PWM_INIT)
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