309 lines
8.9 KiB
C
309 lines
8.9 KiB
C
/*
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* Copyright (c) 2021, STRIM LLC
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*
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* Based on adc_mcux_adc12.c, which are:
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* Copyright (c) 2017-2018, NXP
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_mcux_12b1msps_sar
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#include <drivers/adc.h>
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#include <fsl_adc.h>
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(adc_mcux_12b1msps_sar);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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struct mcux_12b1msps_sar_adc_config {
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ADC_Type *base;
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adc_clock_source_t clock_src;
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adc_clock_driver_t clock_drv;
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adc_reference_voltage_source_t ref_src;
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adc_sample_period_mode_t sample_period_mode;
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void (*irq_config_func)(const struct device *dev);
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};
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struct mcux_12b1msps_sar_adc_data {
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const struct device *dev;
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struct adc_context ctx;
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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uint32_t channels;
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uint8_t channel_id;
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};
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static int mcux_12b1msps_sar_adc_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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uint8_t channel_id = channel_cfg->channel_id;
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if (channel_id > (ADC_HC_ADCH_MASK >> ADC_HC_ADCH_SHIFT)) {
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LOG_ERR("Invalid channel %d", channel_id);
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return -EINVAL;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Unsupported channel acquisition time");
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return -ENOTSUP;
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}
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if (channel_cfg->differential) {
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LOG_ERR("Differential channels are not supported");
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return -ENOTSUP;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
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return -ENOTSUP;
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}
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if (channel_cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Unsupported channel reference");
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return -ENOTSUP;
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}
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return 0;
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}
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static int mcux_12b1msps_sar_adc_start_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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const struct mcux_12b1msps_sar_adc_config *config = dev->config;
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struct mcux_12b1msps_sar_adc_data *data = dev->data;
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adc_hardware_average_mode_t mode;
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adc_resolution_t resolution;
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ADC_Type *base = config->base;
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int error;
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uint32_t tmp32;
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switch (sequence->resolution) {
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case 8:
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resolution = kADC_Resolution8Bit;
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break;
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case 10:
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resolution = kADC_Resolution10Bit;
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break;
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case 12:
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resolution = kADC_Resolution12Bit;
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break;
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default:
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LOG_ERR("Unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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tmp32 = base->CFG & ~(ADC_CFG_MODE_MASK);
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tmp32 |= ADC_CFG_MODE(resolution);
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base->CFG = tmp32;
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switch (sequence->oversampling) {
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case 0:
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mode = kADC_HardwareAverageDiasable;
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break;
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case 2:
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mode = kADC_HardwareAverageCount4;
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break;
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case 3:
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mode = kADC_HardwareAverageCount8;
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break;
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case 4:
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mode = kADC_HardwareAverageCount16;
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break;
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case 5:
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mode = kADC_HardwareAverageCount32;
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break;
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default:
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LOG_ERR("Unsupported oversampling value %d",
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sequence->oversampling);
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return -ENOTSUP;
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}
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ADC_SetHardwareAverageConfig(config->base, mode);
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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error = adc_context_wait_for_completion(&data->ctx);
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return error;
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}
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static int mcux_12b1msps_sar_adc_read_async(const struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct mcux_12b1msps_sar_adc_data *data = dev->data;
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int error;
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adc_context_lock(&data->ctx, async ? true : false, async);
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error = mcux_12b1msps_sar_adc_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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static int mcux_12b1msps_sar_adc_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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return mcux_12b1msps_sar_adc_read_async(dev, sequence, NULL);
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}
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static void mcux_12b1msps_sar_adc_start_channel(const struct device *dev)
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{
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const struct mcux_12b1msps_sar_adc_config *config = dev->config;
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struct mcux_12b1msps_sar_adc_data *data = dev->data;
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adc_channel_config_t channel_config;
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uint32_t channel_group = 0U;
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data->channel_id = find_lsb_set(data->channels) - 1;
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LOG_DBG("Starting channel %d", data->channel_id);
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channel_config.enableInterruptOnConversionCompleted = true;
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channel_config.channelNumber = data->channel_id;
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ADC_SetChannelConfig(config->base, channel_group, &channel_config);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct mcux_12b1msps_sar_adc_data *data =
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CONTAINER_OF(ctx, struct mcux_12b1msps_sar_adc_data, ctx);
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data->channels = ctx->sequence.channels;
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data->repeat_buffer = data->buffer;
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mcux_12b1msps_sar_adc_start_channel(data->dev);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct mcux_12b1msps_sar_adc_data *data =
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CONTAINER_OF(ctx, struct mcux_12b1msps_sar_adc_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static void mcux_12b1msps_sar_adc_isr(const struct device *dev)
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{
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const struct mcux_12b1msps_sar_adc_config *config = dev->config;
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struct mcux_12b1msps_sar_adc_data *data = dev->data;
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ADC_Type *base = config->base;
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uint32_t channel_group = 0U;
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uint16_t result;
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result = ADC_GetChannelConversionValue(base, channel_group);
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LOG_DBG("Finished channel %d. Result is 0x%04x", data->channel_id,
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result);
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*data->buffer++ = result;
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data->channels &= ~BIT(data->channel_id);
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if (data->channels) {
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mcux_12b1msps_sar_adc_start_channel(dev);
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} else {
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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static int mcux_12b1msps_sar_adc_init(const struct device *dev)
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{
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const struct mcux_12b1msps_sar_adc_config *config = dev->config;
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struct mcux_12b1msps_sar_adc_data *data = dev->data;
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ADC_Type *base = config->base;
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adc_config_t adc_config;
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ADC_GetDefaultConfig(&adc_config);
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adc_config.referenceVoltageSource = config->ref_src;
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adc_config.clockSource = config->clock_src;
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adc_config.clockDriver = config->clock_drv;
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adc_config.samplePeriodMode = config->sample_period_mode;
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adc_config.resolution = kADC_Resolution12Bit;
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adc_config.enableContinuousConversion = false;
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adc_config.enableOverWrite = false;
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adc_config.enableHighSpeed = false;
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adc_config.enableLowPower = false;
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adc_config.enableLongSample = false;
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adc_config.enableAsynchronousClockOutput = true;
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ADC_Init(base, &adc_config);
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#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && \
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FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
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ADC_EnableHardwareTrigger(base, false);
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#endif
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if (kStatus_Success == ADC_DoAutoCalibration(base)) {
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LOG_DBG("ADC_DoAutoCalibration() Done.");
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} else {
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LOG_WRN("ADC_DoAutoCalibration() Failed.");
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}
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config->irq_config_func(dev);
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data->dev = dev;
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct adc_driver_api mcux_12b1msps_sar_adc_driver_api = {
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.channel_setup = mcux_12b1msps_sar_adc_channel_setup,
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.read = mcux_12b1msps_sar_adc_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = mcux_12b1msps_sar_adc_read_async,
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#endif
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.ref_internal = 3300,
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};
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#define ASSERT_WITHIN_RANGE(val, min, max, str) \
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BUILD_ASSERT(val >= min && val <= max, str)
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#define ASSERT_RT_ADC_CLK_DIV_VALID(val, str) \
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BUILD_ASSERT(val == 1 || val == 2 || val == 4 || val == 8, str)
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#define TO_RT_ADC_CLOCK_DIV(val) _DO_CONCAT(kADC_ClockDriver, val)
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#define ACD_MCUX_12B1MSPS_SAR_INIT(n) \
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static void mcux_12b1msps_sar_adc_config_func_##n(const struct device *dev); \
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\
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ASSERT_RT_ADC_CLK_DIV_VALID(DT_INST_PROP(n, clk_divider), \
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"Invalid clock divider"); \
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ASSERT_WITHIN_RANGE(DT_INST_PROP(n, sample_period_mode), 0, 3, \
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"Invalid sample period mode"); \
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\
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static const struct mcux_12b1msps_sar_adc_config mcux_12b1msps_sar_adc_config_##n = { \
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.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
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.clock_src = kADC_ClockSourceAD, \
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.clock_drv = \
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TO_RT_ADC_CLOCK_DIV(DT_INST_PROP(n, clk_divider)), \
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.ref_src = kADC_ReferenceVoltageSourceAlt0, \
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.sample_period_mode = DT_INST_PROP(n, sample_period_mode), \
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.irq_config_func = mcux_12b1msps_sar_adc_config_func_##n, \
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}; \
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\
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static struct mcux_12b1msps_sar_adc_data mcux_12b1msps_sar_adc_data_##n = { \
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ADC_CONTEXT_INIT_TIMER(mcux_12b1msps_sar_adc_data_##n, ctx), \
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ADC_CONTEXT_INIT_LOCK(mcux_12b1msps_sar_adc_data_##n, ctx), \
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ADC_CONTEXT_INIT_SYNC(mcux_12b1msps_sar_adc_data_##n, ctx), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &mcux_12b1msps_sar_adc_init, NULL, \
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&mcux_12b1msps_sar_adc_data_##n, &mcux_12b1msps_sar_adc_config_##n, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&mcux_12b1msps_sar_adc_driver_api); \
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\
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static void mcux_12b1msps_sar_adc_config_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
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mcux_12b1msps_sar_adc_isr, DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(ACD_MCUX_12B1MSPS_SAR_INIT)
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