384 lines
10 KiB
C
384 lines
10 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <device.h>
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#include <ioapic.h>
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#include <uart.h>
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#include "qm_uart.h"
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#include "qm_scss.h"
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#include "qm_soc_regs.h"
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#define IIR_IID_NO_INTERRUPT_PENDING 0x01
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#define IIR_IID_RECV_DATA_AVAIL 0x04
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#define IIR_IID_CHAR_TIMEOUT 0x0C
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#define IER_ELSI 0x04
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#define DIVISOR_LOW(baudrate) \
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((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / (16 * baudrate)) & 0xFF)
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#define DIVISOR_HIGH(baudrate) \
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(((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / (16 * baudrate)) & 0xFF00) >> 8)
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/* Convenient macro to get the controller instance. */
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#define GET_CONTROLLER_INSTANCE(dev) \
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(((struct uart_qmsi_config_info *)dev->config->config_info)->instance)
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struct uart_qmsi_config_info {
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qm_uart_t instance;
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clk_periph_t clock_gate;
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uint32_t baud_divisor;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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struct uart_qmsi_drv_data {
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uart_irq_callback_t user_cb;
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uint8_t iir_cache;
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};
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static int uart_qmsi_init(struct device *dev);
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#ifdef CONFIG_UART_QMSI_0
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void irq_config_func_0(struct device *dev);
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static struct uart_qmsi_config_info config_info_0 = {
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.instance = QM_UART_0,
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.clock_gate = CLK_PERIPH_UARTA_REGISTER | CLK_PERIPH_CLK,
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.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(
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DIVISOR_HIGH(CONFIG_UART_QMSI_0_BAUDRATE),
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DIVISOR_LOW(CONFIG_UART_QMSI_0_BAUDRATE),
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0),
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = irq_config_func_0,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static struct uart_qmsi_drv_data drv_data_0;
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DEVICE_INIT(uart_0, CONFIG_UART_QMSI_0_NAME, uart_qmsi_init, &drv_data_0,
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&config_info_0, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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#endif /* CONFIG_UART_QMSI_0 */
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#ifdef CONFIG_UART_QMSI_1
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void irq_config_func_1(struct device *dev);
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static struct uart_qmsi_config_info config_info_1 = {
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.instance = QM_UART_1,
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.clock_gate = CLK_PERIPH_UARTB_REGISTER | CLK_PERIPH_CLK,
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.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(
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DIVISOR_HIGH(CONFIG_UART_QMSI_1_BAUDRATE),
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DIVISOR_LOW(CONFIG_UART_QMSI_1_BAUDRATE),
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0),
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = irq_config_func_1,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static struct uart_qmsi_drv_data drv_data_1;
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DEVICE_INIT(uart_1, CONFIG_UART_QMSI_1_NAME, uart_qmsi_init, &drv_data_1,
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&config_info_1, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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#endif /* CONFIG_UART_QMSI_1 */
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static int uart_qmsi_poll_in(struct device *dev, unsigned char *data)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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qm_uart_status_t status = qm_uart_get_status(instance);
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/* In order to check if there is any data to read from UART
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* controller we should check if the QM_UART_RX_BUSY bit from
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* 'status' is not set. This bit is set only if there is any
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* pending character to read.
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*/
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if (!(status & QM_UART_RX_BUSY))
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return -1;
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qm_uart_read(instance, data);
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return 0;
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}
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static unsigned char uart_qmsi_poll_out(struct device *dev,
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unsigned char data)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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qm_uart_write(instance, data);
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return data;
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}
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static int uart_qmsi_err_check(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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/* QMSI and Zephyr use the same bits to represent UART errors
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* so we don't need to translate each error bit from QMSI API
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* to Zephyr API.
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*/
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return qm_uart_get_status(instance) & QM_UART_LSR_ERROR_BITS;
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}
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#if CONFIG_UART_INTERRUPT_DRIVEN
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static bool is_tx_fifo_full(qm_uart_t instance)
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{
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return !!(QM_UART[instance].lsr & QM_UART_LSR_THRE);
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}
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static int uart_qmsi_fifo_fill(struct device *dev, const uint8_t *tx_data,
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int size)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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int i;
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for (i = 0; i < size && !is_tx_fifo_full(instance); i++) {
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QM_UART[instance].rbr_thr_dll = tx_data[i];
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}
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return i;
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}
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static bool is_data_ready(qm_uart_t instance)
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{
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return QM_UART[instance].lsr & QM_UART_LSR_DR;
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}
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static int uart_qmsi_fifo_read(struct device *dev, uint8_t *rx_data,
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const int size)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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int i;
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for (i = 0; i < size && is_data_ready(instance); i++) {
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rx_data[i] = QM_UART[instance].rbr_thr_dll;
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}
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return i;
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}
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static void uart_qmsi_irq_tx_enable(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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QM_UART[instance].ier_dlh |= QM_UART_IER_ETBEI;
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}
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static void uart_qmsi_irq_tx_disable(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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QM_UART[instance].ier_dlh &= ~QM_UART_IER_ETBEI;
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}
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static int uart_qmsi_irq_tx_ready(struct device *dev)
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{
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struct uart_qmsi_drv_data *drv_data = dev->driver_data;
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uint32_t id = (drv_data->iir_cache & QM_UART_IIR_IID_MASK);
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return id == QM_UART_IIR_THR_EMPTY;
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}
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static int uart_qmsi_irq_tx_empty(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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const uint32_t mask = (QM_UART_LSR_TEMT | QM_UART_LSR_THRE);
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return (QM_UART[instance].lsr & mask) == mask;
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}
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static void uart_qmsi_irq_rx_enable(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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QM_UART[instance].ier_dlh |= QM_UART_IER_ERBFI;
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}
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static void uart_qmsi_irq_rx_disable(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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QM_UART[instance].ier_dlh &= ~QM_UART_IER_ERBFI;
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}
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static int uart_qmsi_irq_rx_ready(struct device *dev)
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{
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struct uart_qmsi_drv_data *drv_data = dev->driver_data;
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uint32_t id = (drv_data->iir_cache & QM_UART_IIR_IID_MASK);
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return (id == IIR_IID_RECV_DATA_AVAIL) || (id == IIR_IID_CHAR_TIMEOUT);
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}
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static void uart_qmsi_irq_err_enable(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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QM_UART[instance].ier_dlh |= IER_ELSI;
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}
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static void uart_qmsi_irq_err_disable(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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QM_UART[instance].ier_dlh &= ~IER_ELSI;
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}
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static int uart_qmsi_irq_is_pending(struct device *dev)
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{
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struct uart_qmsi_drv_data *drv_data = dev->driver_data;
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uint32_t id = (drv_data->iir_cache & QM_UART_IIR_IID_MASK);
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return !(id == IIR_IID_NO_INTERRUPT_PENDING);
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}
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static int uart_qmsi_irq_update(struct device *dev)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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struct uart_qmsi_drv_data *drv_data = dev->driver_data;
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drv_data->iir_cache = QM_UART[instance].iir_fcr;
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return 1;
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}
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static void uart_qmsi_irq_callback_set(struct device *dev,
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uart_irq_callback_t cb)
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{
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struct uart_qmsi_drv_data *drv_data = dev->driver_data;
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drv_data->user_cb = cb;
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}
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static void uart_qmsi_isr(void *arg)
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{
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struct device *dev = arg;
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struct uart_qmsi_drv_data *drv_data = dev->driver_data;
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if (drv_data->user_cb)
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drv_data->user_cb(dev);
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}
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#ifdef CONFIG_UART_QMSI_0
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static void irq_config_func_0(struct device *dev)
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{
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IRQ_CONNECT(QM_IRQ_UART_0, CONFIG_UART_QMSI_0_IRQ_PRI,
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uart_qmsi_isr, DEVICE_GET(uart_0),
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(IOAPIC_LEVEL | IOAPIC_HIGH));
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irq_enable(QM_IRQ_UART_0);
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QM_SCSS_INT->int_uart_0_mask &= ~BIT(0);
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}
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#endif /* CONFIG_UART_QMSI_0 */
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#ifdef CONFIG_UART_QMSI_1
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static void irq_config_func_1(struct device *dev)
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{
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IRQ_CONNECT(QM_IRQ_UART_1, CONFIG_UART_QMSI_1_IRQ_PRI,
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uart_qmsi_isr, DEVICE_GET(uart_1),
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(IOAPIC_LEVEL | IOAPIC_HIGH));
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irq_enable(QM_IRQ_UART_1);
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QM_SCSS_INT->int_uart_1_mask &= ~BIT(0);
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}
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#endif /* CONFIG_UART_QMSI_1 */
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#ifdef CONFIG_UART_LINE_CTRL
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static int uart_qmsi_line_ctrl_set(struct device *dev, uint32_t ctrl, uint32_t val)
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{
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qm_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
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qm_uart_config_t cfg;
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switch (ctrl) {
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case LINE_CTRL_BAUD_RATE:
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qm_uart_get_config(instance, &cfg);
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cfg.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(DIVISOR_HIGH(val),
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DIVISOR_LOW(val), 0);
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qm_uart_set_config(instance, &cfg);
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break;
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default:
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return -ENODEV;
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}
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return 0;
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}
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#endif /* CONFIG_UART_LINE_CTRL */
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#ifdef CONFIG_UART_DRV_CMD
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static int uart_qmsi_drv_cmd(struct device *dev, uint32_t cmd, uint32_t p)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_UART_DRV_CMD */
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static struct uart_driver_api api = {
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.poll_in = uart_qmsi_poll_in,
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.poll_out = uart_qmsi_poll_out,
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.err_check = uart_qmsi_err_check,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_qmsi_fifo_fill,
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.fifo_read = uart_qmsi_fifo_read,
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.irq_tx_enable = uart_qmsi_irq_tx_enable,
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.irq_tx_disable = uart_qmsi_irq_tx_disable,
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.irq_tx_ready = uart_qmsi_irq_tx_ready,
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.irq_tx_empty = uart_qmsi_irq_tx_empty,
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.irq_rx_enable = uart_qmsi_irq_rx_enable,
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.irq_rx_disable = uart_qmsi_irq_rx_disable,
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.irq_rx_ready = uart_qmsi_irq_rx_ready,
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.irq_err_enable = uart_qmsi_irq_err_enable,
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.irq_err_disable = uart_qmsi_irq_err_disable,
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.irq_is_pending = uart_qmsi_irq_is_pending,
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.irq_update = uart_qmsi_irq_update,
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.irq_callback_set = uart_qmsi_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVE */
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#ifdef CONFIG_UART_LINE_CTRL
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.line_ctrl_set = uart_qmsi_line_ctrl_set,
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#endif /* CONFIG_UART_LINE_CTR */
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#ifdef CONFIG_UART_DRV_CMD
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.drv_cmd = uart_qmsi_drv_cmd,
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#endif /* CONFIG_UART_DRV_CMD */
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};
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static int uart_qmsi_init(struct device *dev)
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{
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struct uart_qmsi_config_info *config = dev->config->config_info;
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qm_uart_config_t cfg;
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cfg.line_control = QM_UART_LC_8N1;
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cfg.baud_divisor = config->baud_divisor;
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cfg.hw_fc = false;
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cfg.int_en = false;
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clk_periph_enable(config->clock_gate);
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qm_uart_set_config(config->instance, &cfg);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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config->irq_config_func(dev);
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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dev->driver_api = &api;
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return 0;
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}
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