363 lines
7.7 KiB
C
363 lines
7.7 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Driver for the MMIO-based GPIO driver.
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*/
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#include <errno.h>
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#include <nanokernel.h>
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#include <gpio.h>
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#include "gpio_mmio.h"
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#if defined(CONFIG_GPIO_MMIO_0_ACCESS_MM) \
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|| defined(CONFIG_GPIO_MMIO_1_ACCESS_MM)
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static uint32_t _mm_set_bit(uint32_t addr, uint32_t bit, uint32_t value)
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{
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if (!value) {
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sys_clear_bit(addr, bit);
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} else {
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sys_set_bit(addr, bit);
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}
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return 0;
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}
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static uint32_t _mm_read(uint32_t addr, uint32_t bit, uint32_t value)
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{
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ARG_UNUSED(bit);
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ARG_UNUSED(value);
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return sys_read32(addr);
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}
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static uint32_t _mm_write(uint32_t addr, uint32_t bit, uint32_t value)
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{
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ARG_UNUSED(bit);
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sys_write32(value, addr);
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return 0;
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}
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#endif /* if direct memory access is needed */
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#if defined(CONFIG_GPIO_MMIO_0_ACCESS_IO) \
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|| defined(CONFIG_GPIO_MMIO_1_ACCESS_IO)
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static uint32_t _io_set_bit(uint32_t addr, uint32_t bit, uint32_t value)
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{
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if (!value) {
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sys_io_clear_bit(addr, bit);
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} else {
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sys_io_set_bit(addr, bit);
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}
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return 0;
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}
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static uint32_t _io_read(uint32_t addr, uint32_t bit, uint32_t value)
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{
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ARG_UNUSED(bit);
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ARG_UNUSED(value);
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return sys_in32(addr);
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}
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static uint32_t _io_write(uint32_t addr, uint32_t bit, uint32_t value)
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{
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ARG_UNUSED(bit);
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sys_out32(value, addr);
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return 0;
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}
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#endif /* if io port access is needed */
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/**
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* @brief Configurate pin or port
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_mmio_config(struct device *dev,
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int access_op, uint32_t pin, int flags)
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{
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const struct gpio_mmio_config * const cfg =
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dev->config->config_info;
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uint32_t value = 0;
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/* Setup direction register */
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if (!cfg->reg.dir) {
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return -EINVAL;
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}
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if (cfg->cfg_flags & GPIO_MMIO_CFG_DIR_MASK) {
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/* Direction register is inverse
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* INV: 0 - pin is input, 1 - pin is output
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*/
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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value = 0x0;
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} else {
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value = 0xFFFFFFFF;
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}
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} else {
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/* Direction register is normal.
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* NORMAL: 0 - pin is output, 1 - pin is input
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*/
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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value = 0xFFFFFFFF;
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} else {
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value = 0x0;
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}
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}
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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cfg->access.set_bit(cfg->reg.dir, pin, value);
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break;
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case GPIO_ACCESS_BY_PORT:
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cfg->access.write(cfg->reg.dir, 0, value);
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break;
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default:
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return -ENOTSUP;
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}
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/*
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* Enable the GPIO pin(s), since the direction is
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* also being setup. This indicates pin(s) is being used.
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*
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* This is not really necessary, so don't fail if
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* register is not defined.
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*/
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if (!cfg->reg.en) {
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return 0;
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}
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if (cfg->cfg_flags & GPIO_MMIO_CFG_EN_MASK) {
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/* INV: 0 - enable, 1 - disable */
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value = 0x0;
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} else {
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/* NORMAL: 0 - disable, 1 - enable */
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value = 0xFFFFFFFF;
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}
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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cfg->access.set_bit(cfg->reg.en, pin, value);
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break;
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case GPIO_ACCESS_BY_PORT:
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cfg->access.write(cfg->reg.en, 0, value);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* @brief Set the pin or port output
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param value Value to set (0 or 1)
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_mmio_write(struct device *dev, int access_op,
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uint32_t pin, uint32_t value)
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{
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const struct gpio_mmio_config * const cfg =
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dev->config->config_info;
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if (!cfg->reg.output) {
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return -EINVAL;
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}
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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cfg->access.set_bit(cfg->reg.output, pin, value);
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break;
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case GPIO_ACCESS_BY_PORT:
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cfg->access.write(cfg->reg.output, 0, value);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* @brief Read the pin or port status
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param value Value of input pin(s)
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_mmio_read(struct device *dev,
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int access_op, uint32_t pin, uint32_t *value)
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{
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const struct gpio_mmio_config * const cfg =
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dev->config->config_info;
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if (!cfg->reg.input) {
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return -EINVAL;
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}
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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*value = cfg->access.read(cfg->reg.input, 0, 0);
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*value &= BIT(pin) >> pin;
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break;
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case GPIO_ACCESS_BY_PORT:
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*value = cfg->access.read(cfg->reg.input, 0, 0);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_mmio_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(callback);
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ARG_UNUSED(set);
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return -ENOTSUP;
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}
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static int gpio_mmio_enable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(access_op);
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ARG_UNUSED(pin);
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return -ENOTSUP;
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}
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static int gpio_mmio_disable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(access_op);
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ARG_UNUSED(pin);
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return -ENOTSUP;
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}
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static struct gpio_driver_api gpio_mmio_drv_api_funcs = {
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.config = gpio_mmio_config,
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.write = gpio_mmio_write,
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.read = gpio_mmio_read,
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.manage_callback = gpio_mmio_manage_callback,
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.enable_callback = gpio_mmio_enable_callback,
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.disable_callback = gpio_mmio_disable_callback,
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};
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/**
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* @brief Initialization function of MMIO
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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int gpio_mmio_init(struct device *dev)
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{
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dev->driver_api = &gpio_mmio_drv_api_funcs;
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return 0;
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}
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/* Initialization for MMIO_0 */
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#ifdef CONFIG_GPIO_MMIO_0
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#include <device.h>
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#include <init.h>
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static struct gpio_mmio_config gpio_mmio_0_cfg = {
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.cfg_flags = CONFIG_GPIO_MMIO_0_CFG,
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.reg.en = CONFIG_GPIO_MMIO_0_EN,
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.reg.dir = CONFIG_GPIO_MMIO_0_DIR,
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.reg.input = CONFIG_GPIO_MMIO_0_INPUT,
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.reg.output = CONFIG_GPIO_MMIO_0_OUTPUT,
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#ifdef CONFIG_GPIO_MMIO_0_ACCESS_IO
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.access.set_bit = _io_set_bit,
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.access.read = _io_read,
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.access.write = _io_write,
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#else /* below is for CONFIG_GPIO_MMIO_0_ACCESS_MM=y or else */
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.access.set_bit = _mm_set_bit,
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.access.read = _mm_read,
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.access.write = _mm_write,
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#endif
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};
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DEVICE_INIT(gpio_mmio_0, CONFIG_GPIO_MMIO_0_DEV_NAME, gpio_mmio_init,
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NULL, &gpio_mmio_0_cfg,
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SECONDARY, CONFIG_GPIO_MMIO_INIT_PRIORITY);
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#endif /* CONFIG_GPIO_MMIO_0 */
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/* Initialization for MMIO_1 */
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#ifdef CONFIG_GPIO_MMIO_1
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#include <device.h>
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#include <init.h>
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static struct gpio_mmio_config gpio_mmio_1_cfg = {
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.cfg_flags = CONFIG_GPIO_MMIO_0_CFG,
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.reg.en = CONFIG_GPIO_MMIO_1_EN,
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.reg.dir = CONFIG_GPIO_MMIO_1_DIR,
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.reg.input = CONFIG_GPIO_MMIO_1_INPUT,
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.reg.output = CONFIG_GPIO_MMIO_1_OUTPUT,
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#ifdef CONFIG_GPIO_MMIO_1_ACCESS_IO
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.access.set_bit = _io_set_bit,
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.access.read = _io_read,
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.access.write = _io_write,
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#else /* below is for CONFIG_GPIO_MMIO_1_ACCESS_MM=y or else */
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.access.set_bit = _mm_set_bit,
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.access.read = _mm_read,
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.access.write = _mm_write,
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#endif
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};
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DEVICE_INIT(gpio_mmio_1, CONFIG_GPIO_MMIO_1_DEV_NAME, gpio_mmio_init,
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NULL, &gpio_mmio_1_cfg,
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SECONDARY, CONFIG_GPIO_MMIO_INIT_PRIORITY);
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#endif /* CONFIG_GPIO_MMIO_1 */
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