Anas Nashif c2c6a6a245 qemu_riscv32: use hifive1 configuration ... Use hifive1 configuration for this qemu and set SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000 Fixes #10043 Signed-off-by: Anas Nashif <anas.nashif@intel.com>		2018-11-05 11:00:38 -05:00
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microsemi-miv.dtsi	riscv: Add min dts support for miv SoC & m2gl025_miv board	2018-11-03 06:58:23 -04:00
pulpino.dtsi	dts: pulpino: Add device tree support for GPIO controller	2018-10-04 07:48:32 -05:00
riscv32-fe310.dtsi	gpio: sifive: Add device tree support for GPIO generation	2018-10-05 13:21:49 -05:00