zephyr/boards/arm/mps3_an547/mps3_an547_ns.dts

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/*
* Copyright (c) 2018-2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv8.1-m.dtsi>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <mem.h>
/ {
compatible = "arm,mps3-an547";
#address-cells = <1>;
#size-cells = <1>;
aliases {
led0 = &led_0;
led1 = &led_1;
sw0 = &user_button_0;
sw1 = &user_button_1;
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram;
zephyr,flash = &code;
};
leds {
compatible = "gpio-leds";
led_0: led_0 {
gpios = <&gpio_led0 0>;
label = "USERLED0";
};
led_1: led_1 {
gpios = <&gpio_led0 1>;
label = "USERLED1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_0: button_0 {
label = "USERPB0";
gpios = <&gpio_button 0>;
};
user_button_1: button_1 {
label = "USERPB1";
gpios = <&gpio_button 1>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m55";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8.1m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <16>;
};
};
};
/* We utilize the secure addresses, if you subtract 0x10000000
* you'll get the non-secure alias
*/
itcm: itcm@10000000 { /* alias @ 0x0 */
reg = <0x10000000 DT_SIZE_K(512)>;
};
sram: sram@1000000 { /* alias @ 0x11000000 */
compatible = "mmio-sram";
reg = <0x1000000 DT_SIZE_M(2)>;
};
dtcm: dtcm@20000000 { /* alias @ 0x30000000 */
reg = <0x20000000 DT_SIZE_K(512)>;
};
isram: sram@31000000 {/* alias @ 0x21000000 */
compatible = "mmio-sram";
reg = <0x31000000 DT_SIZE_M(4)>;
};
/* DDR4 - 2G, alternates non-secure/secure every 256M */
ddr4: memory@60000000 {
device_type = "memory";
reg = <0x60000000 DT_SIZE_M(256)
0x70000000 DT_SIZE_M(256)
0x80000000 DT_SIZE_M(256)
0x90000000 DT_SIZE_M(256)
0xa0000000 DT_SIZE_M(256)
0xb0000000 DT_SIZE_M(256)
0xc0000000 DT_SIZE_M(256)
0xd0000000 DT_SIZE_M(256)>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* The memory regions defined below must match what the TF-M
* project has defined for that board - a single image boot is
* assumed. Please see the memory layout in:
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/an547/partition/flash_layout.h
*/
code: memory@01060000 {
reg = <0x01060000 DT_SIZE_K(384)>;
};
ram: memory@21000000 {
reg = <0x21000000 DT_SIZE_M(2)>;
};
};
soc {
peripheral@40000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x40000000 0x10000000>;
#include "mps3_an547-common.dtsi"
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};