143 lines
2.8 KiB
Plaintext
143 lines
2.8 KiB
Plaintext
/*
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* Copyright (c) 2018-2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm/armv8.1-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <mem.h>
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/ {
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compatible = "arm,mps3-an547";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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led0 = &led_0;
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led1 = &led_1;
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sw0 = &user_button_0;
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sw1 = &user_button_1;
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};
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &ram;
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zephyr,flash = &code;
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};
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leds {
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compatible = "gpio-leds";
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led_0: led_0 {
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gpios = <&gpio_led0 0>;
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label = "USERLED0";
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};
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led_1: led_1 {
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gpios = <&gpio_led0 1>;
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label = "USERLED1";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_0: button_0 {
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label = "USERPB0";
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gpios = <&gpio_button 0>;
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};
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user_button_1: button_1 {
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label = "USERPB1";
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gpios = <&gpio_button 1>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m55";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8.1m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <16>;
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};
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};
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};
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/* We utilize the secure addresses, if you subtract 0x10000000
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* you'll get the non-secure alias
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*/
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itcm: itcm@10000000 { /* alias @ 0x0 */
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reg = <0x10000000 DT_SIZE_K(512)>;
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};
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sram: sram@1000000 { /* alias @ 0x11000000 */
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compatible = "mmio-sram";
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reg = <0x1000000 DT_SIZE_M(2)>;
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};
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dtcm: dtcm@20000000 { /* alias @ 0x30000000 */
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reg = <0x20000000 DT_SIZE_K(512)>;
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};
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isram: sram@31000000 {/* alias @ 0x21000000 */
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compatible = "mmio-sram";
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reg = <0x31000000 DT_SIZE_M(4)>;
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};
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/* DDR4 - 2G, alternates non-secure/secure every 256M */
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ddr4: memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 DT_SIZE_M(256)
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0x70000000 DT_SIZE_M(256)
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0x80000000 DT_SIZE_M(256)
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0x90000000 DT_SIZE_M(256)
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0xa0000000 DT_SIZE_M(256)
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0xb0000000 DT_SIZE_M(256)
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0xc0000000 DT_SIZE_M(256)
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0xd0000000 DT_SIZE_M(256)>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* The memory regions defined below must match what the TF-M
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* project has defined for that board - a single image boot is
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* assumed. Please see the memory layout in:
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* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/an547/partition/flash_layout.h
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*/
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code: memory@01060000 {
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reg = <0x01060000 DT_SIZE_K(384)>;
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};
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ram: memory@21000000 {
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reg = <0x21000000 DT_SIZE_M(2)>;
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};
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};
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soc {
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peripheral@40000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x40000000 0x10000000>;
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#include "mps3_an547-common.dtsi"
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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