195 lines
5.6 KiB
ReStructuredText
195 lines
5.6 KiB
ReStructuredText
.. _dragino_lsn50_board:
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Dragino LSN50 LoRA Sensor Node
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##############################
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Overview
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********
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The Dragino LSN50 LoRA Sensor Node for IoT allows users to develop
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applications with LoraWAN connectivity via the HopeRF / SX1276/SX1278.
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Dragino LSN50 enables a wide diversity of applications by exploiting
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low-power communication, ARM |reg| Cortex |reg|-M0 core-based
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STM32L0 Series features.
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This kit provides:
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- STM32L072CZ MCU
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- SX1276/SX1278 LoRa Transceiver
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- Expansion connectors:
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- PMOD
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- Li/SOCI2 Unchargable Battery
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- GPIOs exposed via screw terminals on the carrier board
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- Housing
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.. image:: img/dragino_lsn50.jpg
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:align: center
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:alt: Dragino LSN50
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More information about the board can be found at the `Dragino LSN50 website`_.
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Hardware
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********
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The STM32L072CZ SoC provides the following hardware IPs:
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- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode)
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- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz
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- Clock Sources:
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- 1 to 32 MHz crystal oscillator
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- 32 kHz crystal oscillator for RTC (LSE)
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- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
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- Internal low-power 37 kHz RC ( |plusminus| 5%)
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- Internal multispeed low-power 65 kHz to 4.2 MHz RC
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- RTC with HW calendar, alarms and calibration
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- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
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- 11x timers:
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- 2x 16-bit with up to 4 channels
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- 2x 16-bit with up to 2 channels
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- 1x 16-bit ultra-low-power timer
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- 1x SysTick
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- 1x RTC
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- 2x 16-bit basic for DAC
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- 2x watchdogs (independent/window)
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- Up to 84 fast I/Os, most 5 V-tolerant.
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- Memories
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- Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection
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- Up to 20 KB of SRAM
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- External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories
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- Rich analog peripherals (independent supply)
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- 1x 12-bit ADC 1.14 MSPS
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- 2x 12-bit DAC
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- 2x ultra-low-power comparators
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- 11x communication interfaces
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- USB OTG 2.0 full-speed, LPM and BCD
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- 3x I2C FM+(1 Mbit/s), SMBus/PMBus
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- 4x USARTs (ISO 7816, LIN, IrDA, modem)
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- 6x SPIs (4x SPIs with the Quad SPI)
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- 7-channel DMA controller
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- True random number generator
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- CRC calculation unit, 96-bit unique ID
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- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
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More information about STM32L072CZ can be found here:
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- `STM32L072CZ on www.st.com`_
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- `STM32L0x2 reference manual`_
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Supported Features
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==================
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The Zephyr Dragino LSN50 Board board configuration supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on this Zephyr port.
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The default configuration can be found in the defconfig file:
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``boards/arm/dragino_lsn50/dragino_lsn50_defconfig``
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Connections and IOs
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===================
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Dragino LSN50 Board has GPIO controllers. These controllers are responsible for pin muxing,
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input/output, pull-up, etc.
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Available pins:
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---------------
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For detailed information about available pins please refer to `Dragino LSN50 website`_.
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Default Zephyr Peripheral Mapping:
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----------------------------------
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- UART_1_TX : PB6
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- UART_1_RX : PB7
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- UART_2_TX : PA2
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- UART_2_RX : PA3
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System Clock
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------------
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Dragino LSN50 System Clock is at 32MHz,
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Serial Port
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-----------
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Dragino LSN50 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1.
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Default settings are 115200 8N1.
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Programming and Debugging
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*************************
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Applications for the ``dragino_lsn50`` board configuration can be built and
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flashed in the usual way (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Flashing
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========
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Dragino LSN50 board requires an external debugger.
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Flashing an application to Dragino LSN50
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----------------------------------------
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Here is an example for the :ref:`hello_world` application.
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Connect the Dragino LSN50 to a STLinkV2 to your host computer using the USB port, then
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run a serial host program to connect with your board. For example:
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.. code-block:: console
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$ minicom -D /dev/ttyACM0
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Then build and flash the application:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: dragino_lsn50
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:goals: build flash
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You should see the following message on the console:
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.. code-block:: console
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$ Hello World! arm
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Debugging
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=========
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You can debug an application in the usual way. Here is an example for the
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:ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: dragino_lsn50
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:maybe-skip-config:
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:goals: debug
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.. _Dragino LSN50 website:
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https://www.dragino.com/products/lora-lorawan-end-node/item/128-lsn50.html
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.. _STM32L072CZ on www.st.com:
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http://www.st.com/en/microcontrollers/stm32l072cz.html
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.. _STM32L0x2 reference manual:
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http://www.st.com/resource/en/reference_manual/DM00108281.pdf
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