127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
/*
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* Copyright (c) 2021 Telink Semiconductor
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sys.h"
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#include "clock.h"
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#include <device.h>
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/* Software reset defines */
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#define reg_reset REG_ADDR8(0x1401ef)
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#define SOFT_RESET 0x20u
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/* List of supported CCLK fregencies */
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#define CLK_16MHZ 16000000u
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#define CLK_24MHZ 24000000u
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#define CLK_32MHZ 32000000u
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#define CLK_48MHZ 48000000u
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#define CLK_64MHZ 64000000u
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#define CLK_96MHZ 96000000u
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/* Define 48 MHz and 96 MHz CCLK clock options (not present in HAL) */
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#define CCLK_64M_HCLK_32M_PCLK_16M clock_init(PLL_CLK_192M, \
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PAD_PLL_DIV, \
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PLL_DIV3_TO_CCLK, \
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CCLK_DIV2_TO_HCLK, \
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HCLK_DIV2_TO_PCLK, \
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PLL_DIV4_TO_MSPI_CLK)
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#define CCLK_96M_HCLK_48M_PCLK_24M clock_init(PLL_CLK_192M, \
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PAD_PLL_DIV, \
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PLL_DIV2_TO_CCLK, \
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CCLK_DIV2_TO_HCLK, \
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HCLK_DIV2_TO_PCLK, \
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PLL_DIV4_TO_MSPI_CLK)
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/* Power Mode value */
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#if DT_ENUM_IDX(DT_NODELABEL(power), power_mode) == 0
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#define POWER_MODE LDO_1P4_LDO_1P8
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#elif DT_ENUM_IDX(DT_NODELABEL(power), power_mode) == 1
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#define POWER_MODE DCDC_1P4_LDO_1P8
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#elif DT_ENUM_IDX(DT_NODELABEL(power), power_mode) == 2
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#define POWER_MODE DCDC_1P4_DCDC_1P8
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#else
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#error "Wrong value for power-mode parameter"
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#endif
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/* Vbat Type value */
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#if DT_ENUM_IDX(DT_NODELABEL(power), vbat_type) == 0
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#define VBAT_TYPE VBAT_MAX_VALUE_LESS_THAN_3V6
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#elif DT_ENUM_IDX(DT_NODELABEL(power), vbat_type) == 1
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#define VBAT_TYPE VBAT_MAX_VALUE_GREATER_THAN_3V6
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#else
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#error "Wrong value for vbat-type parameter"
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#endif
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/* Check System Clock value. */
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#if ((DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_16MHZ) && \
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(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_24MHZ) && \
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(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_32MHZ) && \
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(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_48MHZ) && \
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(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_64MHZ) && \
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(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_96MHZ))
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#error "Unsupported clock-frequency. Supported values: 16, 24, 32, 48, 64 and 96 MHz"
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#endif
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/**
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* @brief Perform basic initialization at boot.
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*
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* @return 0
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*/
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static int soc_b91_init(const struct device *arg)
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{
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unsigned int cclk = DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency);
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ARG_UNUSED(arg);
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/* system init */
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sys_init(POWER_MODE, VBAT_TYPE);
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/* clocks init: CCLK, HCLK, PCLK */
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switch (cclk) {
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case CLK_16MHZ:
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CCLK_16M_HCLK_16M_PCLK_16M;
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break;
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case CLK_24MHZ:
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CCLK_24M_HCLK_24M_PCLK_24M;
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break;
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case CLK_32MHZ:
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CCLK_32M_HCLK_32M_PCLK_16M;
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break;
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case CLK_48MHZ:
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CCLK_48M_HCLK_48M_PCLK_24M;
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break;
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case CLK_64MHZ:
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CCLK_64M_HCLK_32M_PCLK_16M;
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break;
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case CLK_96MHZ:
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CCLK_96M_HCLK_48M_PCLK_24M;
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break;
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}
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/* Init Machine Timer source clock: 32 KHz RC */
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clock_32k_init(CLK_32K_RC);
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clock_cal_32k_rc();
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return 0;
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}
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/**
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* @brief Reset the system.
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*/
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void sys_arch_reboot(int type)
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{
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ARG_UNUSED(type);
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reg_reset = SOFT_RESET;
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}
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SYS_INIT(soc_b91_init, PRE_KERNEL_1, 0);
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