111 lines
4.1 KiB
C
111 lines
4.1 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_STM32_PINCTRLF1_H_
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#define ZEPHYR_STM32_PINCTRLF1_H_
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#include <dt-bindings/pinctrl/stm32-pinctrl-common.h>
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/**
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* @brief PIN configuration bitfield
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*
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* Pin configuration is coded with the following
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* fields
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* GPIO I/O Mode [ 0 ]
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* GPIO Input config [ 1 : 2 ]
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* GPIO Output speed [ 3 : 4 ]
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* GPIO Output PP/OD [ 5 ]
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* GPIO Output AF/GP [ 6 ]
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* GPIO PUPD Config [ 7 : 8 ]
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*
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* Applicable to STM32F1 series
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*/
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/* Alternate functions */
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/* STM32F1 Pinmux doesn't use explicit alternate functions */
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/* These are kept for compatibility with other STM32 pinmux */
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#define STM32_AFR_MASK 0
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#define STM32_AFR_SHIFT 0
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/* Port Mode */
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#define STM32_MODE_INPUT (0x0<<STM32_MODE_INOUT_SHIFT)
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#define STM32_MODE_OUTPUT (0x1<<STM32_MODE_INOUT_SHIFT)
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#define STM32_MODE_INOUT_MASK 0x1
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#define STM32_MODE_INOUT_SHIFT 0
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/* Input Port configuration */
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#define STM32_CNF_IN_ANALOG (0x0<<STM32_CNF_IN_SHIFT)
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#define STM32_CNF_IN_FLOAT (0x1<<STM32_CNF_IN_SHIFT)
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#define STM32_CNF_IN_PUPD (0x2<<STM32_CNF_IN_SHIFT)
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#define STM32_CNF_IN_MASK 0x3
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#define STM32_CNF_IN_SHIFT 1
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/* Output Port configuration */
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#define STM32_MODE_OUTPUT_MAX_10 (0x0<<STM32_MODE_OSPEED_SHIFT)
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#define STM32_MODE_OUTPUT_MAX_2 (0x1<<STM32_MODE_OSPEED_SHIFT)
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#define STM32_MODE_OUTPUT_MAX_50 (0x2<<STM32_MODE_OSPEED_SHIFT)
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#define STM32_MODE_OSPEED_MASK 0x3
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#define STM32_MODE_OSPEED_SHIFT 3
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#define STM32_CNF_PUSH_PULL (0x0<<STM32_CNF_OUT_0_SHIFT)
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#define STM32_CNF_OPEN_DRAIN (0x1<<STM32_CNF_OUT_0_SHIFT)
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#define STM32_CNF_OUT_0_MASK 0x1
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#define STM32_CNF_OUT_0_SHIFT 5
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#define STM32_CNF_GP_OUTPUT (0x0<<STM32_CNF_OUT_1_SHIFT)
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#define STM32_CNF_ALT_FUNC (0x1<<STM32_CNF_OUT_1_SHIFT)
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#define STM32_CNF_OUT_1_MASK 0x1
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#define STM32_CNF_OUT_1_SHIFT 6
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/* GPIO High impedance/Pull-up/Pull-down */
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#define STM32_PUPD_NO_PULL (0x0<<STM32_PUPD_SHIFT)
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#define STM32_PUPD_PULL_UP (0x1<<STM32_PUPD_SHIFT)
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#define STM32_PUPD_PULL_DOWN (0x2<<STM32_PUPD_SHIFT)
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#define STM32_PUPD_MASK 0x3
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#define STM32_PUPD_SHIFT 7
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/* Alternate defines */
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/* IO pin functions are mostly common across STM32 devices. Notable
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* exception is STM32F1 as these MCUs do not have registers for
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* configuration of pin's alternate function. The configuration is
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* done implicitly by setting specific mode and config in MODE and CNF
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* registers for particular pin.
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*/
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#define STM32_PIN_USART_TX (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL | STM32_PUPD_PULL_UP)
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#define STM32_PIN_USART_RX (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_I2C (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_OPEN_DRAIN)
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#define STM32_PIN_PWM (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_SPI_MASTER_SCK (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_SPI_SLAVE_SCK (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_SPI_MASTER_MOSI (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_SPI_SLAVE_MOSI (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_SPI_MASTER_MISO (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_SPI_SLAVE_MISO (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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/*
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* Reference manual (RM0008)
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* Section 25.3.1: Slave select (NSS) pin management
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*
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* Hardware NSS management:
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* - NSS output disabled: allows multimaster capability for devices operating
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* in master mode.
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* - NSS output enabled: used only when the device operates in master mode.
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*
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* Software NSS management:
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* - External NSS pin remains free for other application uses.
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*
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*/
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/* Hardware master NSS output disabled */
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#define STM32_PIN_SPI_MASTER_NSS (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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/* Hardware master NSS output enabled */
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#define STM32_PIN_SPI_MASTER_NSS_OE (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC | STM32_CNF_PUSH_PULL)
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#define STM32_PIN_SPI_SLAVE_NSS (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
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#define STM32_PIN_USB (STM32_MODE_INPUT | STM32_CNF_IN_PUPD)
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#endif /* ZEPHYR_STM32_PINCTRLF1_H_ */
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