203 lines
4.8 KiB
C
203 lines
4.8 KiB
C
/**
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* Copyright (c) 2015-2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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*
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* @brief Designware ADC header file
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*/
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#ifndef ZEPHYR_DRIVERS_ADC_ADC_INTEL_QUARK_SE_C1000_SS_H_
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#define ZEPHYR_DRIVERS_ADC_ADC_INTEL_QUARK_SE_C1000_SS_H_
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#include <zephyr/types.h>
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#include <drivers/adc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* ADC driver name.
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*
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* Name for the singleton instance of the ADC driver.
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*
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*/
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#define ADC_DRV_NAME "adc"
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/**
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* Number of buffers.
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*
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* Number of reception buffers to be supported by the driver.
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*/
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#define BUFS_NUM 32
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/* EAI ADC device registers */
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#define ADC_SET (0x00)
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#define ADC_DIVSEQSTAT (0x01)
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#define ADC_SEQ (0x02)
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#define ADC_CTRL (0x03)
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#define ADC_INTSTAT (0x04)
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#define ADC_SAMPLE (0x05)
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/* Sensor Subsystem Interrupt Routing Mask */
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#define INT_SS_ADC_ERR_MASK (0x400)
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#define INT_SS_ADC_IRQ_MASK (0x404)
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/* ADC_DIVSEQSTAT register */
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#define ADC_DIVSEQSTAT_CLK_RATIO_MASK (0x1fffff)
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/* ADC_SET register */
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#define ADC_SET_POP_RX BIT(31)
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#define ADC_SET_FLUSH_RX BIT(30)
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#define ADC_SET_SEQ_MODE_MASK BIT(13)
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#define ADC_SET_INPUT_MODE_MASK BIT(5)
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#define ADC_SET_THRESHOLD_MASK (0x3F000000)
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#define ADC_SET_THRESHOLD_POS 24
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#define ADC_SET_SEQ_ENTRIES_MASK (0x003F0000)
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#define ADC_SET_SEQ_ENTRIES_POS 16
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/* ADC_CTRL register */
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#define ADC_CTRL_CLR_DATA_A BIT(16)
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#define ADC_CTRL_SEQ_TABLE_RST BIT(6)
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#define ADC_CTRL_SEQ_PTR_RST BIT(5)
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#define ADC_CTRL_SEQ_START BIT(4)
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#define ADC_CTRL_CLK_ENABLE BIT(2)
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#define ADC_CTRL_INT_CLR_ALL (0x000F0000)
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#define ADC_CTRL_INT_MASK_ALL (0x00000F00)
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#define ADC_CTRL_ENABLE BIT(1)
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#define ADC_CTRL_DISABLE (0x0)
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/* ADC_INTSTAT register */
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#define ADC_INTSTAT_SEQERROR BIT(3)
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#define ADC_INTSTAT_UNDERFLOW BIT(2)
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#define ADC_INTSTAT_OVERFLOW BIT(1)
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#define ADC_INTSTAT_DATA_A BIT(0)
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#define ADC_STATE_CLOSED 0
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#define ADC_STATE_DISABLED 1
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#define ADC_STATE_IDLE 2
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#define ADC_STATE_SAMPLING 3
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#define ADC_STATE_ERROR 4
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#define ADC_CMD_RESET_CALIBRATION 2
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#define ADC_CMD_START_CALIBRATION 3
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#define ADC_CMD_LOAD_CALIBRATION 4
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#define IO_ADC_SET_CLK_DIVIDER (0x20)
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#define IO_ADC_SET_CONFIG (0x21)
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#define IO_ADC_SET_SEQ_TABLE (0x22)
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#define IO_ADC_SET_SEQ_MODE (0x23)
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#define IO_ADC_SET_SEQ_STOP (0x24)
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#define IO_ADC_SET_RX_THRESHOLD (0x25)
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#define IO_ADC_INPUT_SINGLE_END 0
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#define IO_ADC_INPUT_DIFF 1
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#define IO_ADC_OUTPUT_PARAL 0
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#define IO_ADC_OUTPUT_SERIAL 1
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#define IO_ADC_CAPTURE_RISING_EDGE 0
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#define IO_ADC_CAPTURE_FALLING_EDGE 1
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#define IO_ADC_SEQ_MODE_SINGLESHOT 0
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#define IO_ADC_SEQ_MODE_REPETITIVE 1
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#define ENABLE_SSS_INTERRUPTS ~(0x01 << 8)
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#define ENABLE_ADC \
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( \
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ADC_CTRL_CLK_ENABLE \
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| ADC_CTRL_SEQ_TABLE_RST \
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| ADC_CTRL_SEQ_PTR_RST \
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)
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#define START_ADC_SEQ \
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( \
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ADC_CTRL_SEQ_START \
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| ADC_CTRL_ENABLE \
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| ADC_CTRL_CLK_ENABLE \
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)
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#define DW_CHANNEL_COUNT 19
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/** mV = 3.3V*/
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#define ADC_VREF 3300
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/**
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*
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* @brief Converts ADC raw data into mV
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*
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* The ADC raw data readings are converted into mV:
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* result = (data * ADC_VREF) / (2^resolution).
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*
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* @param _data_ Raw data to be converted.
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* @param _resolution_ Resolution used during the data sampling.
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*
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* @return data read in mVolts.
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*/
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#define ss_adc_data_to_mv(_data_, _resolution_) \
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((_data_ * ADC_VREF) / (1 << _resolution_))
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typedef void (*adc_intel_quark_se_c1000_ss_config_t)(void);
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/** @brief ADC configuration
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* This structure defines the ADC configuration values
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* that define the ADC hardware instance and configuration.
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*/
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struct adc_config {
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/**Register base address for hardware registers.*/
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u32_t reg_base;
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/**IIO address for the IRQ mask register.*/
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u32_t reg_irq_mask;
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/**IIO address for the error mask register.*/
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u32_t reg_err_mask;
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/**Output mode*/
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u8_t out_mode;
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/**Capture mode*/
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u8_t capture_mode;
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/**Sequence mode*/
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u8_t seq_mode;
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/**Serial delay*/
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u8_t serial_dly;
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/**Sample width*/
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u8_t sample_width;
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u8_t padding[3];
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/**Clock ratio*/
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u32_t clock_ratio;
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/**Config handler*/
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adc_intel_quark_se_c1000_ss_config_t config_func;
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};
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/**@brief ADC information and data.
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*
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* This structure defines the data that will be used
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* during driver execution.
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*/
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struct adc_info {
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struct device *dev;
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struct adc_context ctx;
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u16_t *buffer;
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u32_t active_channels;
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u32_t channels;
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u32_t channel_id;
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/**Sequence entries' array*/
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const struct adc_sequence *entries;
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/**State of execution of the driver*/
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u8_t state;
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/**Sequence size*/
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u8_t seq_size;
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#ifdef CONFIG_ADC_INTEL_QUARK_SE_C1000_SS_CALIBRATION
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/**Calibration value*/
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u8_t calibration_value;
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#endif
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_ADC_ADC_INTEL_QUARK_SE_C1000_SS_H_ */
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