282 lines
6.4 KiB
C
282 lines
6.4 KiB
C
/*
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* Copyright (c) 2018 Justin Watson
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* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam4l_gpio
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <drivers/gpio.h>
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#include "gpio_utils.h"
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typedef void (*config_func_t)(const struct device *dev);
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struct gpio_sam_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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Gpio *regs;
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config_func_t config_func;
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uint32_t periph_id;
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};
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struct gpio_sam_runtime {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t cb;
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};
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#define DEV_CFG(dev) \
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((const struct gpio_sam_config * const)(dev)->config)
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#define DEV_DATA(dev) \
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((struct gpio_sam_runtime * const)(dev)->data)
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#define GPIO_SAM_ALL_PINS 0xFFFFFFFF
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static int gpio_sam_port_configure(const struct device *dev,
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uint32_t mask,
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gpio_flags_t flags)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Gpio * const gpio = cfg->regs;
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/* No hardware support */
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if (flags & GPIO_SINGLE_ENDED) {
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return -ENOTSUP;
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}
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if (!(flags & (GPIO_OUTPUT | GPIO_INPUT))) {
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gpio->IERC = mask;
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gpio->PUERC = mask;
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gpio->PDERC = mask;
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gpio->GPERS = mask;
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gpio->ODERC = mask;
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gpio->STERC = mask;
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return 0;
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}
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/*
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* Always enable schmitt-trigger because SAM4L GPIO Ctrl
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* is Input only or Input/Output.
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*/
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gpio->STERS = mask;
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio->OVRS = mask;
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio->OVRC = mask;
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}
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gpio->ODERS = mask;
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} else {
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gpio->ODERC = mask;
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}
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gpio->PUERC = mask;
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gpio->PDERC = mask;
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if (flags & GPIO_PULL_UP) {
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gpio->PUERS = mask;
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} else if (flags & GPIO_PULL_DOWN) {
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gpio->PDERS = mask;
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}
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/* Enable the GPIO to control the pin (instead of a peripheral). */
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gpio->GPERS = mask;
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return 0;
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}
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static int gpio_sam_config(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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return gpio_sam_port_configure(dev, BIT(pin), flags);
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}
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static int gpio_sam_port_get_raw(const struct device *dev,
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uint32_t *value)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Gpio * const gpio = cfg->regs;
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*value = gpio->PVR;
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return 0;
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}
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static int gpio_sam_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Gpio * const gpio = cfg->regs;
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gpio->OVR = (gpio->PVR & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_sam_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Gpio * const gpio = cfg->regs;
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gpio->OVRS = mask;
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return 0;
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}
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static int gpio_sam_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Gpio * const gpio = cfg->regs;
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gpio->OVRC = mask;
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return 0;
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}
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static int gpio_sam_port_toggle_bits(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Gpio * const gpio = cfg->regs;
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gpio->OVRT = mask;
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return 0;
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}
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static int gpio_sam_port_interrupt_configure(const struct device *dev,
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uint32_t mask,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Gpio * const gpio = cfg->regs;
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if (mode == GPIO_INT_MODE_LEVEL) {
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return -ENOTSUP;
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}
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gpio->IERC = mask;
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gpio->IMR0C = mask;
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gpio->IMR1C = mask;
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if (trig != GPIO_INT_TRIG_BOTH) {
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if (trig == GPIO_INT_TRIG_HIGH) {
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gpio->IMR0S = mask;
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} else {
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gpio->IMR1S = mask;
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}
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}
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if (mode != GPIO_INT_MODE_DISABLED) {
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gpio->IFRC = mask;
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gpio->IERS = mask;
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}
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return 0;
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}
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static int gpio_sam_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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return gpio_sam_port_interrupt_configure(dev, BIT(pin), mode, trig);
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}
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static void gpio_sam_isr(const struct device *dev)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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Gpio * const gpio = cfg->regs;
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struct gpio_sam_runtime *context = dev->data;
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uint32_t int_stat;
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int_stat = gpio->IFR;
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gpio->IFRC = int_stat;
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gpio_fire_callbacks(&context->cb, dev, int_stat);
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}
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static int gpio_sam_manage_callback(const struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_sam_runtime *context = port->data;
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return gpio_manage_callback(&context->cb, callback, set);
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}
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static const struct gpio_driver_api gpio_sam_api = {
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.pin_configure = gpio_sam_config,
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.port_get_raw = gpio_sam_port_get_raw,
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.port_set_masked_raw = gpio_sam_port_set_masked_raw,
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.port_set_bits_raw = gpio_sam_port_set_bits_raw,
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.port_clear_bits_raw = gpio_sam_port_clear_bits_raw,
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.port_toggle_bits = gpio_sam_port_toggle_bits,
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.pin_interrupt_configure = gpio_sam_pin_interrupt_configure,
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.manage_callback = gpio_sam_manage_callback,
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};
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int gpio_sam_init(const struct device *dev)
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{
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const struct gpio_sam_config * const cfg = DEV_CFG(dev);
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soc_pmc_peripheral_enable(cfg->periph_id);
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cfg->config_func(dev);
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return 0;
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}
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#define GPIO_SAM_IRQ_CONNECT(n, m) \
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do { \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
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DT_INST_IRQ_BY_IDX(n, m, priority), \
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gpio_sam_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
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} while (0)
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#define GPIO_SAM_INIT(n) \
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static void port_##n##_sam_config_func(const struct device *dev);\
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\
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static const struct gpio_sam_config port_##n##_sam_config = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
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}, \
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.regs = (Gpio *)DT_INST_REG_ADDR(n), \
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.periph_id = DT_INST_PROP(n, peripheral_id), \
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.config_func = port_##n##_sam_config_func, \
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}; \
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\
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static struct gpio_sam_runtime port_##n##_sam_runtime; \
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\
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DEVICE_DT_INST_DEFINE(n, gpio_sam_init, NULL, \
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&port_##n##_sam_runtime, \
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&port_##n##_sam_config, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&gpio_sam_api); \
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\
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static void port_##n##_sam_config_func(const struct device *dev)\
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{ \
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GPIO_SAM_IRQ_CONNECT(n, 0); \
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GPIO_SAM_IRQ_CONNECT(n, 1); \
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GPIO_SAM_IRQ_CONNECT(n, 2); \
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GPIO_SAM_IRQ_CONNECT(n, 3); \
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}
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DT_INST_FOREACH_STATUS_OKAY(GPIO_SAM_INIT)
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