60 lines
1.1 KiB
Plaintext
60 lines
1.1 KiB
Plaintext
/*
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* Copyright (c) 2020 Jonas Eriksson, Up to Code AB
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*
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* SoC device tree include for STM32F100xB SoCs
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/f1/stm32f1.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(8)>;
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};
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clocks {
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/delete-node/ pll;
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32f100-pll-clock";
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status = "disabled";
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};
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};
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soc {
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compatible = "st,stm32f100", "st,stm32f1", "simple-bus";
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(128)>;
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erase-block-size = <DT_SIZE_K(1)>;
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};
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
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interrupts = <36 5>;
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status = "disabled";
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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};
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die_temp: dietemp {
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v25 = <1410>;
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};
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};
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