327 lines
6.3 KiB
C
327 lines
6.3 KiB
C
/*
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* Copyright (c) 2021-2022 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT xlnx_fpga
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#include <zephyr/device.h>
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#include <zephyr/drivers/fpga.h>
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#include "fpga_zynqmp.h"
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#include <errno.h>
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#include <string.h>
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#include <zephyr/sys/byteorder.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(fpga_zynqmp);
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static void power_up_fpga(void)
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{
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PMU_GLOBAL_PWRUP_EN = PWR_PL_MASK;
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PMU_REQ_PWRUP_TRIG = PWR_PL_MASK;
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while (PWR_STATUS & PWR_PL_MASK) {
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};
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}
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struct zynqmp_fpga_data {
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char FPGA_info[16];
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};
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static void update_part_name(const struct device *dev)
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{
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struct zynqmp_fpga_data *data = dev->data;
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int zu_number = 0;
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switch (IDCODE & IDCODE_MASK) {
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case ZU2_IDCODE:
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zu_number = 2;
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break;
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case ZU3_IDCODE:
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zu_number = 3;
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break;
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case ZU4_IDCODE:
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zu_number = 4;
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break;
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case ZU5_IDCODE:
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zu_number = 5;
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break;
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case ZU6_IDCODE:
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zu_number = 6;
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break;
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case ZU7_IDCODE:
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zu_number = 7;
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break;
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case ZU9_IDCODE:
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zu_number = 9;
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break;
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case ZU11_IDCODE:
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zu_number = 11;
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break;
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case ZU15_IDCODE:
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zu_number = 15;
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break;
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case ZU17_IDCODE:
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zu_number = 17;
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break;
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case ZU19_IDCODE:
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zu_number = 19;
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break;
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case ZU21_IDCODE:
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zu_number = 21;
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break;
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case ZU25_IDCODE:
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zu_number = 25;
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break;
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case ZU27_IDCODE:
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zu_number = 27;
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break;
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case ZU28_IDCODE:
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zu_number = 28;
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break;
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case ZU29_IDCODE:
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zu_number = 29;
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break;
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case ZU39_IDCODE:
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zu_number = 39;
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break;
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case ZU43_IDCODE:
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zu_number = 43;
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break;
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case ZU46_IDCODE:
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zu_number = 46;
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break;
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case ZU47_IDCODE:
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zu_number = 47;
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break;
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case ZU48_IDCODE:
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zu_number = 48;
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break;
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case ZU49_IDCODE:
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zu_number = 49;
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break;
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}
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if (zu_number == 0) {
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snprintf(data->FPGA_info, sizeof(data->FPGA_info), "unknown");
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} else {
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snprintf(data->FPGA_info, sizeof(data->FPGA_info), "Part name: ZU%d", zu_number);
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}
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}
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/*
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* This function is responsible for shifting the bitstream
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* by its header and extracting information from this header.
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* The bitstream header has 5 sections starting with the letters a,b,c...
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* Each section has the following structure:
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* [key][length of data][data]
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*/
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static uint32_t *parse_header(const struct device *dev, uint32_t *image_ptr,
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uint32_t *img_size)
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{
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unsigned char *header = (unsigned char *)image_ptr;
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uint32_t length = XLNX_BITSTREAM_SECTION_LENGTH(header);
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/* shift to the next section*/
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header += 0x4U + length;
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if (*header++ != 'a') {
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LOG_ERR("Incorrect bitstream format");
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return NULL;
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}
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length = XLNX_BITSTREAM_SECTION_LENGTH(header);
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/* shift to the data section*/
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header += 0x2U;
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LOG_DBG("Design name = %s", header);
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header += length;
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if (*header++ != 'b') {
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LOG_ERR("Incorrect bitstream format");
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return NULL;
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}
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length = XLNX_BITSTREAM_SECTION_LENGTH(header);
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/* shift to the data section*/
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header += 0x2U;
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LOG_DBG("Part name = %s", header);
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header += length;
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if (*header++ != 'c') {
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LOG_ERR("Incorrect bitstream format");
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return NULL;
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}
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length = XLNX_BITSTREAM_SECTION_LENGTH(header);
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/* shift to the data section*/
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header += 0x2U;
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LOG_DBG("Date = %s", header);
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header += length;
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if (*header++ != 'd') {
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LOG_ERR("Incorrect bitstream format");
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return NULL;
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}
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length = XLNX_BITSTREAM_SECTION_LENGTH(header);
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/* shift to the data section*/
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header += 0x2U;
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LOG_DBG("Time = %s", header);
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header += length;
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if (*header++ != 'e') {
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LOG_ERR("Incorrect bitstream format");
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return NULL;
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}
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/*
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* The last section is the raw bitstream.
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* It is preceded by its size, which is needed for DMA transfer.
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*/
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*img_size =
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((uint32_t)*header << 24) | ((uint32_t) *(header + 1) << 16) |
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((uint32_t) *(header + 2) << 8) | ((uint32_t) *(header + 3));
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return (uint32_t *)header;
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}
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static int csudma_transfer(uint32_t size)
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{
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/* setup the source DMA channel */
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CSUDMA_SRC_ADDR = (uint32_t)BITSTREAM & CSUDMA_SRC_ADDR_MASK;
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CSUDMA_SRC_ADDR_MSB = 0;
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CSUDMA_SRC_SIZE = size << CSUDMA_SRC_SIZE_SHIFT;
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/* wait for the SRC_DMA to complete */
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while ((CSUDMA_SRC_I_STS & CSUDMA_I_STS_DONE_MASK) != CSUDMA_I_STS_DONE_MASK) {
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};
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/* acknowledge the transfer has completed */
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CSUDMA_SRC_I_STS = CSUDMA_I_STS_DONE_MASK;
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return 0;
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}
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static int wait_for_done(void)
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{
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/* wait for PCAP PL_DONE */
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while ((PCAP_STATUS & PCAP_PL_DONE_MASK) != PCAP_PL_DONE_MASK) {
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};
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PCAP_RESET = PCAP_RESET_MASK;
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power_up_fpga();
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return 0;
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}
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static enum FPGA_status zynqmp_fpga_get_status(const struct device *dev)
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{
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ARG_UNUSED(dev);
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if ((PCAP_STATUS & PCAP_PL_INIT_MASK) && (PCAP_STATUS & PCAP_PL_DONE_MASK)) {
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return FPGA_STATUS_ACTIVE;
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} else {
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return FPGA_STATUS_INACTIVE;
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}
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}
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static const char *zynqmp_fpga_get_info(const struct device *dev)
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{
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struct zynqmp_fpga_data *data = dev->data;
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return data->FPGA_info;
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}
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static int zynqmp_fpga_reset(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* Reset PL */
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PCAP_PROG = PCAP_PROG_RESET_MASK;
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PCAP_PROG = ~PCAP_PROG_RESET_MASK;
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while ((PCAP_STATUS & PCAP_CFG_RESET) != PCAP_CFG_RESET) {
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};
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return 0;
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}
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static int init_pcap(const struct device *dev)
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{
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/* take PCAP out of Reset */
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PCAP_RESET = ~PCAP_RESET_MASK;
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/* select PCAP mode and change PCAP to write mode */
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PCAP_CTRL = PCAP_PR_MASK;
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PCAP_RDWR = PCAP_WRITE_MASK;
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power_up_fpga();
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/* setup the SSS */
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CSU_SSS_CFG = PCAP_PCAP_SSS_MASK;
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zynqmp_fpga_reset(dev);
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/* wait for pl init */
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while ((PCAP_STATUS & PCAP_PL_INIT_MASK) != PCAP_PL_INIT_MASK) {
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};
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return 0;
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}
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static int zynqmp_fpga_load(const struct device *dev, uint32_t *image_ptr,
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uint32_t img_size)
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{
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uint32_t *addr = parse_header(dev, image_ptr, &img_size);
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if (addr == NULL) {
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LOG_ERR("Failed to read bitstream");
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return -EINVAL;
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}
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for (int i = 0; i < (img_size / 4); i++) {
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*(BITSTREAM + i) = __bswap_32(*(addr + i));
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}
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init_pcap(dev);
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csudma_transfer(img_size);
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wait_for_done();
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return 0;
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}
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static int zynqmp_fpga_init(const struct device *dev)
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{
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/* turn on PCAP CLK */
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PCAP_CLK_CTRL = PCAP_CLK_CTRL | PCAP_CLKACT_MASK;
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update_part_name(dev);
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return 0;
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}
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static struct zynqmp_fpga_data fpga_data;
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static const struct fpga_driver_api zynqmp_api = {
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.reset = zynqmp_fpga_reset,
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.load = zynqmp_fpga_load,
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.get_status = zynqmp_fpga_get_status,
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.get_info = zynqmp_fpga_get_info
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};
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DEVICE_DT_INST_DEFINE(0, &zynqmp_fpga_init, NULL, &fpga_data, NULL,
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POST_KERNEL, CONFIG_FPGA_INIT_PRIORITY, &zynqmp_api);
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