112 lines
2.4 KiB
C
112 lines
2.4 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/kernel.h>
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#include <zephyr/spinlock.h>
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#include <soc.h>
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#include <counter/counter_ace_v1x_art_regs.h>
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static struct k_spinlock lock;
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static void counter_ace_v1x_art_ionte_set(bool new_timestamp_enable)
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{
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uint32_t val;
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val = sys_read32(ACE_TSCTRL);
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val &= ~ACE_TSCTRL_IONTE_MASK;
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val |= FIELD_PREP(ACE_TSCTRL_IONTE_MASK, new_timestamp_enable);
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sys_write32(val, ACE_TSCTRL);
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}
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static void counter_ace_v1x_art_cdmas_set(uint32_t cdmas)
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{
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uint32_t val;
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val = sys_read32(ACE_TSCTRL);
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val &= ~ACE_TSCTRL_CDMAS_MASK;
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val |= FIELD_PREP(ACE_TSCTRL_CDMAS_MASK, cdmas);
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sys_write32(val, ACE_TSCTRL);
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}
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static void counter_ace_v1x_art_ntk_set(bool new_timestamp_taken)
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{
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uint32_t val;
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val = sys_read32(ACE_TSCTRL);
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val &= ~ACE_TSCTRL_NTK_MASK;
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val |= FIELD_PREP(ACE_TSCTRL_NTK_MASK, new_timestamp_taken);
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sys_write32(val, ACE_TSCTRL);
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}
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static uint32_t counter_ace_v1x_art_ntk_get(void)
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{
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return FIELD_GET(ACE_TSCTRL_NTK_MASK, sys_read32(ACE_TSCTRL));
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}
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static void counter_ace_v1x_art_hhtse_set(bool enable)
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{
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uint32_t val;
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val = sys_read32(ACE_TSCTRL);
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val &= ~ACE_TSCTRL_HHTSE_MASK;
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val |= FIELD_PREP(ACE_TSCTRL_HHTSE_MASK, enable);
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sys_write32(val, ACE_TSCTRL);
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}
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static uint64_t counter_ace_v1x_art_counter_get(void)
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{
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uint32_t hi0, lo, hi1;
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do {
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hi0 = sys_read32(ACE_ARTCS_HI);
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lo = sys_read32(ACE_ARTCS_LO);
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hi1 = sys_read32(ACE_ARTCS_HI);
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} while (hi0 != hi1);
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return (((uint64_t)hi1) << 32) | lo;
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}
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int counter_ace_v1x_art_get_value(const struct device *dev, uint64_t *value)
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{
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ARG_UNUSED(dev);
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k_spinlock_key_t key = k_spin_lock(&lock);
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counter_ace_v1x_art_ionte_set(1);
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counter_ace_v1x_art_cdmas_set(1);
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if (counter_ace_v1x_art_ntk_get()) {
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counter_ace_v1x_art_ntk_set(1);
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while (counter_ace_v1x_art_ntk_get()) {
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k_busy_wait(10);
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}
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}
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counter_ace_v1x_art_hhtse_set(1);
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while (!counter_ace_v1x_art_ntk_get()) {
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k_busy_wait(10);
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}
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*value = counter_ace_v1x_art_counter_get();
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counter_ace_v1x_art_ntk_set(1);
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k_spin_unlock(&lock, key);
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return 0;
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}
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static const struct counter_driver_api ace_v1x_art_counter_apis = {
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.get_value_64 = counter_ace_v1x_art_get_value
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(ace_art_counter), NULL, NULL, NULL, NULL,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&ace_v1x_art_counter_apis);
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