169 lines
4.2 KiB
Plaintext
169 lines
4.2 KiB
Plaintext
# Atmel SAM V71 MCU series
|
|
|
|
# Copyright (c) 2019 Gerson Fernando Budke
|
|
# Copyright (c) 2016 Piotr Mienkowski
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
choice
|
|
prompt "Atmel SAMV71 MCU Selection"
|
|
depends on SOC_SERIES_SAMV71
|
|
|
|
config SOC_PART_NUMBER_SAMV71Q21
|
|
bool "SAMV71Q21"
|
|
|
|
config SOC_PART_NUMBER_SAMV71Q20
|
|
bool "SAMV71Q20"
|
|
|
|
config SOC_PART_NUMBER_SAMV71Q19
|
|
bool "SAMV71Q19"
|
|
|
|
config SOC_PART_NUMBER_SAMV71N21
|
|
bool "SAMV71N21"
|
|
|
|
config SOC_PART_NUMBER_SAMV71N20
|
|
bool "SAMV71N20"
|
|
|
|
config SOC_PART_NUMBER_SAMV71N19
|
|
bool "SAMV71N19"
|
|
|
|
config SOC_PART_NUMBER_SAMV71J21
|
|
bool "SAMV71J21"
|
|
|
|
config SOC_PART_NUMBER_SAMV71J20
|
|
bool "SAMV71J20"
|
|
|
|
config SOC_PART_NUMBER_SAMV71J19
|
|
bool "SAMV71J19"
|
|
|
|
config SOC_PART_NUMBER_SAMV71Q21B
|
|
bool "SAMV71Q21B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
|
|
config SOC_PART_NUMBER_SAMV71Q20B
|
|
bool "SAMV71Q20B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
|
|
config SOC_PART_NUMBER_SAMV71Q19B
|
|
bool "SAMV71Q19B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
|
|
config SOC_PART_NUMBER_SAMV71N21B
|
|
bool "SAMV71N21B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
|
|
config SOC_PART_NUMBER_SAMV71N20B
|
|
bool "SAMV71N20B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
|
|
config SOC_PART_NUMBER_SAMV71N19B
|
|
bool "SAMV71N19B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
|
|
config SOC_PART_NUMBER_SAMV71J21B
|
|
bool "SAMV71J21B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
|
|
config SOC_PART_NUMBER_SAMV71J20B
|
|
bool "SAMV71J20B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
|
|
config SOC_PART_NUMBER_SAMV71J19B
|
|
bool "SAMV71J19B"
|
|
select SOC_ATMEL_SAMV71_REVB
|
|
endchoice
|
|
|
|
if SOC_SERIES_SAMV71
|
|
|
|
config SOC_ATMEL_SAMV71_REVB
|
|
bool
|
|
|
|
config SOC_ATMEL_SAMV71_EXT_SLCK
|
|
bool "Use external crystal oscillator for slow clock"
|
|
help
|
|
Say y if you want to use external 32 kHz crystal
|
|
oscillator to drive the slow clock. Note that this
|
|
adds a few seconds to boot time, as the crystal
|
|
needs to stabilize after power-up.
|
|
|
|
Says n if you do not need accurate and precise timers.
|
|
The slow clock will be driven by the internal fast
|
|
RC oscillator running at 32 kHz.
|
|
|
|
config SOC_ATMEL_SAMV71_EXT_MAINCK
|
|
bool "Use external crystal oscillator for main clock"
|
|
help
|
|
The main clock is being used to drive the PLL, and
|
|
thus driving the processor clock.
|
|
|
|
Say y if you want to use external crystal oscillator
|
|
to drive the main clock. Note that this adds about
|
|
a second to boot time, as the crystal needs to
|
|
stabilize after power-up.
|
|
|
|
The crystal used here can be from 3 to 20 MHz.
|
|
|
|
Says n here will use the internal fast RC oscillator
|
|
running at 12 MHz.
|
|
|
|
config SOC_ATMEL_SAMV71_MDIV
|
|
int "MDIV"
|
|
default 2
|
|
range 1 4
|
|
help
|
|
This divisor defines a ratio between processor clock (HCLK)
|
|
and master clock (MCK):
|
|
MCK = HCLK / MDIV
|
|
|
|
config SOC_ATMEL_SAMV71_PLLA_MULA
|
|
int "PLL MULA"
|
|
default 24
|
|
range 1 62
|
|
help
|
|
This is the multiplier MULA used by the PLL.
|
|
The processor clock is (MAINCK * (MULA + 1) / DIVA).
|
|
|
|
Board config file can override this settings
|
|
for a particular board.
|
|
|
|
Setting MULA=0 would disable PLL at boot, this is currently
|
|
not supported.
|
|
|
|
With default of MULA == 24, and DIVA == 1,
|
|
PLL is running at 25 times the main clock frequency.
|
|
|
|
config SOC_ATMEL_SAMV71_PLLA_DIVA
|
|
int "PLL DIVA"
|
|
default 1
|
|
range 1 255
|
|
help
|
|
This is the divider DIVA used by the PLL.
|
|
The processor clock is (MAINCK * (MULA + 1) / DIVA).
|
|
|
|
Board config file can override this settings
|
|
for a particular board.
|
|
|
|
Setting DIVA=0 would disable PLL at boot, this is currently
|
|
not supported.
|
|
|
|
With default of MULA == 24, and DIVA == 1,
|
|
PLL is running at 25 times the main clock frequency.
|
|
|
|
config SOC_ATMEL_SAMV71_WAIT_MODE
|
|
bool "Go to Wait mode instead of Sleep mode"
|
|
depends on SOC_ATMEL_SAMV71_EXT_MAINCK
|
|
default y if DEBUG
|
|
help
|
|
For JTAG debugging CPU clock (HCLK) should not stop. In order
|
|
to achieve this, make CPU go to Wait mode instead of Sleep
|
|
mode while using external crystal oscillator for main clock.
|
|
|
|
config SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN
|
|
bool "Disable ERASE pin"
|
|
help
|
|
At reset ERASE pin is configured in System IO mode. Asserting the ERASE
|
|
pin at '1' will completely erase Flash memory. Setting this option will
|
|
switch the pin to general IO mode giving control of the pin to the GPIO
|
|
module.
|
|
|
|
endif # SOC_SERIES_SAMV71
|