222 lines
6.3 KiB
C
222 lines
6.3 KiB
C
/*
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* Copyright (c) 2022 Vestas Wind Systems A/S
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* Copyright (c) 2020 Alexander Wachter
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#include <stm32_ll_rcc.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include "can_mcan.h"
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LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT st_stm32_fdcan
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/* This symbol takes the value 1 if one of the device instances */
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/* is configured in dts with a domain clock */
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#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32_CANFD_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define STM32_CANFD_DOMAIN_CLOCK_SUPPORT 0
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#endif
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struct can_stm32fd_config {
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size_t pclk_len;
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const struct stm32_pclken *pclken;
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void (*config_irq)(void);
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const struct pinctrl_dev_config *pcfg;
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uint8_t clock_divider;
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};
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static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
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ARG_UNUSED(dev);
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if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
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LOG_ERR("Can't read core clock");
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return -EIO;
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}
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if (FDCAN_CONFIG->CKDIV == 0) {
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*rate = rate_tmp;
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} else {
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*rate = rate_tmp / (FDCAN_CONFIG->CKDIV << 1);
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}
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return 0;
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}
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static int can_stm32fd_clock_enable(const struct device *dev)
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{
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int ret;
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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if (!device_is_ready(clk)) {
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return -ENODEV;
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}
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if (IS_ENABLED(STM32_CANFD_DOMAIN_CLOCK_SUPPORT) && (stm32fd_cfg->pclk_len > 1)) {
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ret = clock_control_configure(clk,
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(clock_control_subsys_t)&stm32fd_cfg->pclken[1],
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NULL);
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if (ret < 0) {
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LOG_ERR("Could not select can_stm32fd domain clock");
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return ret;
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}
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}
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ret = clock_control_on(clk, (clock_control_subsys_t)&stm32fd_cfg->pclken[0]);
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if (ret < 0) {
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return ret;
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}
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if (stm32fd_cfg->clock_divider != 0) {
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can_mcan_enable_configuration_change(dev);
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FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1;
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}
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return 0;
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}
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static int can_stm32fd_init(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
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int ret;
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/* Configure dt provided device signals when available */
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ret = pinctrl_apply_state(stm32fd_cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("CAN pinctrl setup failed (%d)", ret);
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return ret;
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}
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ret = can_stm32fd_clock_enable(dev);
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if (ret < 0) {
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LOG_ERR("Could not turn on CAN clock (%d)", ret);
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return ret;
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}
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ret = can_mcan_init(dev);
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if (ret != 0) {
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return ret;
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}
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stm32fd_cfg->config_irq();
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return ret;
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}
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static const struct can_driver_api can_stm32fd_driver_api = {
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.get_capabilities = can_mcan_get_capabilities,
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.start = can_mcan_start,
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.stop = can_mcan_stop,
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.set_mode = can_mcan_set_mode,
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.set_timing = can_mcan_set_timing,
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.send = can_mcan_send,
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.add_rx_filter = can_mcan_add_rx_filter,
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.remove_rx_filter = can_mcan_remove_rx_filter,
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.get_state = can_mcan_get_state,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
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.get_core_clock = can_stm32fd_get_core_clock,
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.get_max_bitrate = can_mcan_get_max_bitrate,
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.get_max_filters = can_mcan_get_max_filters,
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.set_state_change_callback = can_mcan_set_state_change_callback,
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.timing_min = {
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.sjw = 0x01,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_max = {
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.sjw = 0x80,
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.prop_seg = 0x00,
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.phase_seg1 = 0x100,
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.phase_seg2 = 0x80,
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.prescaler = 0x200
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},
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#ifdef CONFIG_CAN_FD_MODE
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.set_timing_data = can_mcan_set_timing_data,
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.timing_data_min = {
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.sjw = 0x01,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_data_max = {
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.sjw = 0x10,
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.prop_seg = 0x00,
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.phase_seg1 = 0x20,
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.phase_seg2 = 0x10,
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.prescaler = 0x20
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}
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#endif /* CONFIG_CAN_FD_MODE */
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};
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#define CAN_STM32FD_IRQ_CFG_FUNCTION(inst) \
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static void config_can_##inst##_irq(void) \
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{ \
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LOG_DBG("Enable CAN" #inst " IRQ"); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_0, priority), \
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can_mcan_line_0_isr, DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_1, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_1, priority), \
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can_mcan_line_1_isr, DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_1, irq)); \
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}
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#define CAN_STM32FD_CFG_INST(inst) \
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PINCTRL_DT_INST_DEFINE(inst); \
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static const struct stm32_pclken can_stm32fd_pclken_##inst[] = \
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STM32_DT_INST_CLOCKS(inst); \
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\
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static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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.pclken = can_stm32fd_pclken_##inst, \
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.pclk_len = DT_INST_NUM_CLOCKS(inst), \
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.config_irq = config_can_##inst##_irq, \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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.clock_divider = DT_INST_PROP_OR(inst, clk_divider, 0) \
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}; \
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\
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static const struct can_mcan_config can_mcan_cfg_##inst = \
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CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_stm32fd_cfg_##inst);
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#define CAN_STM32FD_DATA_INST(inst) \
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static struct can_mcan_data can_mcan_data_##inst = \
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CAN_MCAN_DATA_INITIALIZER((struct can_mcan_msg_sram *) \
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DT_INST_REG_ADDR_BY_NAME(inst, message_ram), \
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NULL);
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#define CAN_STM32FD_DEVICE_INST(inst) \
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DEVICE_DT_INST_DEFINE(inst, &can_stm32fd_init, NULL, \
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&can_mcan_data_##inst, &can_mcan_cfg_##inst, \
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POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_stm32fd_driver_api);
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#define CAN_STM32FD_INST(inst) \
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CAN_STM32FD_IRQ_CFG_FUNCTION(inst) \
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CAN_STM32FD_CFG_INST(inst) \
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CAN_STM32FD_DATA_INST(inst) \
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CAN_STM32FD_DEVICE_INST(inst)
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DT_INST_FOREACH_STATUS_OKAY(CAN_STM32FD_INST)
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