334 lines
8.4 KiB
C
334 lines
8.4 KiB
C
/*
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* Copyright (c) 2019 Brett Witherspoon
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc13xx_cc26xx_spi
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_cc13xx_cc26xx);
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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#include <driverlib/prcm.h>
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#include <driverlib/ssi.h>
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#include <ti/drivers/Power.h>
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#include <ti/drivers/power/PowerCC26X2.h>
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#include "spi_context.h"
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struct spi_cc13xx_cc26xx_config {
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uint32_t base;
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const struct pinctrl_dev_config *pcfg;
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};
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struct spi_cc13xx_cc26xx_data {
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struct spi_context ctx;
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};
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#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
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static int spi_cc13xx_cc26xx_configure(const struct device *dev,
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const struct spi_config *config)
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{
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const struct spi_cc13xx_cc26xx_config *cfg = dev->config;
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struct spi_cc13xx_cc26xx_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint32_t prot;
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int ret;
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if (spi_context_configured(ctx, config)) {
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return 0;
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}
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if (config->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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/* Slave mode has not been implemented */
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if (SPI_OP_MODE_GET(config->operation) != SPI_OP_MODE_MASTER) {
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LOG_ERR("Slave mode is not supported");
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return -ENOTSUP;
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}
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/* Word sizes other than 8 bits has not been implemented */
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if (SPI_WORD_SIZE_GET(config->operation) != 8) {
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LOG_ERR("Word sizes other than 8 bits are not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("Transfer LSB first mode is not supported");
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return -EINVAL;
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}
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if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
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(config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Multiple lines are not supported");
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return -EINVAL;
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}
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if (config->operation & SPI_CS_ACTIVE_HIGH && !spi_cs_is_gpio(config)) {
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LOG_ERR("Active high CS requires emulation through a GPIO line.");
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return -EINVAL;
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}
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if (config->frequency < 2000000) {
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LOG_ERR("Frequencies lower than 2 MHz are not supported");
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return -EINVAL;
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}
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if (2 * config->frequency > CPU_FREQ) {
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LOG_ERR("Frequency greater than supported in master mode");
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return -EINVAL;
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}
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) {
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
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prot = SSI_FRF_MOTO_MODE_3;
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} else {
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prot = SSI_FRF_MOTO_MODE_2;
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}
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} else {
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
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prot = SSI_FRF_MOTO_MODE_1;
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} else {
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prot = SSI_FRF_MOTO_MODE_0;
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}
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}
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("applying SPI pinctrl state failed");
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return ret;
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}
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ctx->config = config;
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/* Disable SSI before making configuration changes */
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SSIDisable(cfg->base);
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/* Configure SSI */
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SSIConfigSetExpClk(cfg->base, CPU_FREQ, prot,
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SSI_MODE_MASTER, config->frequency, 8);
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if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) {
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sys_set_bit(cfg->base + SSI_O_CR1, 0);
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}
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/* Re-enable SSI after making configuration changes */
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SSIEnable(cfg->base);
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return 0;
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}
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static int spi_cc13xx_cc26xx_transceive(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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const struct spi_cc13xx_cc26xx_config *cfg = dev->config;
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struct spi_cc13xx_cc26xx_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint32_t txd, rxd;
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int err;
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spi_context_lock(ctx, false, NULL, NULL, config);
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pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
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err = spi_cc13xx_cc26xx_configure(dev, config);
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if (err) {
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goto done;
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}
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spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(ctx, true);
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do {
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if (spi_context_tx_buf_on(ctx)) {
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txd = *ctx->tx_buf;
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} else {
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txd = 0U;
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}
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SSIDataPut(cfg->base, txd);
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spi_context_update_tx(ctx, 1, 1);
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SSIDataGet(cfg->base, &rxd);
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if (spi_context_rx_buf_on(ctx)) {
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*ctx->rx_buf = rxd;
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}
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spi_context_update_rx(ctx, 1, 1);
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} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
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spi_context_cs_control(ctx, false);
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done:
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pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
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spi_context_release(ctx, err);
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return err;
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}
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static int spi_cc13xx_cc26xx_release(const struct device *dev,
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const struct spi_config *config)
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{
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const struct spi_cc13xx_cc26xx_config *cfg = dev->config;
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struct spi_cc13xx_cc26xx_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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if (!spi_context_configured(ctx, config)) {
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return -EINVAL;
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}
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if (SSIBusy(cfg->base)) {
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(ctx);
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return 0;
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}
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#ifdef CONFIG_PM_DEVICE
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static int spi_cc13xx_cc26xx_pm_action(const struct device *dev,
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enum pm_device_action action)
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{
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const struct spi_cc13xx_cc26xx_config *config = dev->config;
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switch (action) {
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case PM_DEVICE_ACTION_RESUME:
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if (config->base == DT_INST_REG_ADDR(0)) {
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Power_setDependency(PowerCC26XX_PERIPH_SSI0);
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} else {
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Power_setDependency(PowerCC26XX_PERIPH_SSI1);
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}
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break;
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case PM_DEVICE_ACTION_SUSPEND:
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SSIDisable(config->base);
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/*
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* Release power dependency
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*/
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if (config->base == DT_INST_REG_ADDR(0)) {
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Power_releaseDependency(PowerCC26XX_PERIPH_SSI0);
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} else {
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Power_releaseDependency(PowerCC26XX_PERIPH_SSI1);
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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#endif /* CONFIG_PM_DEVICE */
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static const struct spi_driver_api spi_cc13xx_cc26xx_driver_api = {
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.transceive = spi_cc13xx_cc26xx_transceive,
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.release = spi_cc13xx_cc26xx_release,
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};
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#ifdef CONFIG_PM
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#define SPI_CC13XX_CC26XX_POWER_SPI(n) \
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do { \
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/* Set Power dependencies & constraints */ \
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if (DT_INST_REG_ADDR(n) == 0x40000000) { \
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Power_setDependency(PowerCC26XX_PERIPH_SSI0); \
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} else { \
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Power_setDependency(PowerCC26XX_PERIPH_SSI1); \
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} \
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} while (false)
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#else
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#define SPI_CC13XX_CC26XX_POWER_SPI(n) \
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do { \
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uint32_t domain, periph; \
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\
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/* Enable UART power domain */ \
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if (DT_INST_REG_ADDR(n) == 0x40000000) { \
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domain = PRCM_DOMAIN_SERIAL; \
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periph = PRCM_PERIPH_SSI0; \
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} else { \
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domain = PRCM_DOMAIN_PERIPH; \
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periph = PRCM_PERIPH_SSI1; \
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} \
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/* Enable SSI##n power domain */ \
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PRCMPowerDomainOn(domain); \
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\
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/* Enable SSI##n peripherals */ \
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PRCMPeripheralRunEnable(periph); \
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PRCMPeripheralSleepEnable(periph); \
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PRCMPeripheralDeepSleepEnable(periph); \
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\
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/* Load PRCM settings */ \
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PRCMLoadSet(); \
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while (!PRCMLoadGet()) { \
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continue; \
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} \
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\
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/* SSI should not be accessed until power domain is on. */\
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while (PRCMPowerDomainsAllOn(domain) != \
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PRCM_DOMAIN_POWER_ON) { \
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continue; \
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} \
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} while (false)
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#endif
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#define SPI_CC13XX_CC26XX_DEVICE_INIT(n) \
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PM_DEVICE_DT_INST_DEFINE(n, spi_cc13xx_cc26xx_pm_action); \
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\
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DEVICE_DT_INST_DEFINE(n, \
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spi_cc13xx_cc26xx_init_##n, \
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PM_DEVICE_DT_INST_GET(n), \
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&spi_cc13xx_cc26xx_data_##n, &spi_cc13xx_cc26xx_config_##n, \
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POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
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&spi_cc13xx_cc26xx_driver_api)
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#define SPI_CC13XX_CC26XX_INIT_FUNC(n) \
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static int spi_cc13xx_cc26xx_init_##n(const struct device *dev) \
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{ \
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struct spi_cc13xx_cc26xx_data *data = dev->data; \
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int err; \
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SPI_CC13XX_CC26XX_POWER_SPI(n); \
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\
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err = spi_context_cs_configure_all(&data->ctx); \
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if (err < 0) { \
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return err; \
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} \
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\
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spi_context_unlock_unconditionally(&data->ctx); \
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\
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return 0; \
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}
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#define SPI_CC13XX_CC26XX_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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SPI_CC13XX_CC26XX_INIT_FUNC(n) \
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\
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static const struct spi_cc13xx_cc26xx_config \
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spi_cc13xx_cc26xx_config_##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n) \
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}; \
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\
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static struct spi_cc13xx_cc26xx_data \
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spi_cc13xx_cc26xx_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_cc13xx_cc26xx_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_cc13xx_cc26xx_data_##n, ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
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}; \
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\
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SPI_CC13XX_CC26XX_DEVICE_INIT(n);
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DT_INST_FOREACH_STATUS_OKAY(SPI_CC13XX_CC26XX_INIT)
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