265 lines
7.6 KiB
C
265 lines
7.6 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_spi
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_ambiq);
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/byteorder.h>
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#include <stdlib.h>
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#include <errno.h>
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#include "spi_context.h"
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#include <am_mcu_apollo.h>
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#define PWRCTRL_MAX_WAIT_US 5
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typedef int (*ambiq_spi_pwr_func_t)(void);
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struct spi_ambiq_config {
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uint32_t base;
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int size;
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uint32_t clock_freq;
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const struct pinctrl_dev_config *pcfg;
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ambiq_spi_pwr_func_t pwr_func;
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};
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struct spi_ambiq_data {
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struct spi_context ctx;
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am_hal_iom_config_t iom_cfg;
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void *IOMHandle;
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};
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#define SPI_BASE (((const struct spi_ambiq_config *)(dev)->config)->base)
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#define REG_STAT 0x248
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#define IDLE_STAT 0x4
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#define SPI_STAT(dev) (SPI_BASE + REG_STAT)
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#define SPI_WORD_SIZE 8
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static int spi_config(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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const struct spi_ambiq_config *cfg = dev->config;
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struct spi_context *ctx = &(data->ctx);
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data->iom_cfg.eInterfaceMode = AM_HAL_IOM_SPI_MODE;
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int ret = 0;
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if (spi_context_configured(ctx, config)) {
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/* Already configured. No need to do it again. */
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return 0;
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}
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if (config->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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if (SPI_WORD_SIZE_GET(config->operation) != 8) {
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LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
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return -ENOTSUP;
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}
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if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only supports single mode");
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return -ENOTSUP;
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}
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if (config->operation & SPI_LOCK_ON) {
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LOG_ERR("Lock On not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("LSB first not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_MODE_CPOL) {
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if (config->operation & SPI_MODE_CPHA) {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_3;
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} else {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_2;
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}
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} else {
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if (config->operation & SPI_MODE_CPHA) {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_1;
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} else {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_0;
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}
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}
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if (config->operation & SPI_OP_MODE_SLAVE) {
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LOG_ERR("Slave mode not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode not supported");
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return -ENOTSUP;
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}
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if (cfg->clock_freq > AM_HAL_IOM_MAX_FREQ) {
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LOG_ERR("Clock frequency too high");
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return -ENOTSUP;
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}
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data->iom_cfg.ui32ClockFreq = cfg->clock_freq;
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ctx->config = config;
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/* Disable IOM instance as it cannot be configured when enabled*/
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ret = am_hal_iom_disable(data->IOMHandle);
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ret = am_hal_iom_configure(data->IOMHandle, &data->iom_cfg);
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ret = am_hal_iom_enable(data->IOMHandle);
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return ret;
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}
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static int spi_ambiq_xfer(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int ret = 0;
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am_hal_iom_transfer_t trans = {0};
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if (ctx->tx_len) {
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trans.ui64Instr = *ctx->tx_buf;
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trans.ui32InstrLen = 1;
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spi_context_update_tx(ctx, 1, 1);
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if (ctx->rx_buf != NULL) {
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if (ctx->tx_len > 0) {
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/* The instruction length can only be 0~5. */
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if (ctx->tx_len > 4) {
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spi_context_complete(ctx, dev, 0);
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return -ENOTSUP;
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}
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/* Put the remaining TX data in instruction. */
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trans.ui32InstrLen += ctx->tx_len;
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for (int i = 0; i < trans.ui32InstrLen - 1; i++) {
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trans.ui64Instr = (trans.ui64Instr << 8) | (*ctx->tx_buf);
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spi_context_update_tx(ctx, 1, 1);
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}
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}
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/* Set RX direction and hold CS to continue to receive data. */
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trans.eDirection = AM_HAL_IOM_RX;
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trans.bContinue = true;
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trans.pui32RxBuffer = (uint32_t *)ctx->rx_buf;
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trans.ui32NumBytes = ctx->rx_len;
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ret = am_hal_iom_blocking_transfer(data->IOMHandle, &trans);
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} else if (ctx->tx_buf != NULL) {
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/* Set TX direction to send data and release CS after transmission. */
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trans.eDirection = AM_HAL_IOM_TX;
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trans.bContinue = false;
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trans.ui32NumBytes = ctx->tx_len;
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trans.pui32TxBuffer = (uint32_t *)ctx->tx_buf;
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ret = am_hal_iom_blocking_transfer(data->IOMHandle, &trans);
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}
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} else {
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/* Set RX direction to receive data and release CS after transmission. */
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trans.ui64Instr = 0;
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trans.ui32InstrLen = 0;
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trans.eDirection = AM_HAL_IOM_RX;
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trans.bContinue = false;
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trans.pui32RxBuffer = (uint32_t *)ctx->rx_buf;
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trans.ui32NumBytes = ctx->rx_len;
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ret = am_hal_iom_blocking_transfer(data->IOMHandle, &trans);
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}
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spi_context_complete(ctx, dev, 0);
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return ret;
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}
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static int spi_ambiq_transceive(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_ambiq_data *data = dev->data;
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int ret;
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ret = spi_config(dev, config);
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if (ret) {
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return ret;
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}
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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ret = spi_ambiq_xfer(dev, config);
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return ret;
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}
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static int spi_ambiq_release(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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if (!sys_read32(SPI_STAT(dev))) {
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct spi_driver_api spi_ambiq_driver_api = {
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.transceive = spi_ambiq_transceive,
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.release = spi_ambiq_release,
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};
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static int spi_ambiq_init(const struct device *dev)
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{
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struct spi_ambiq_data *data = dev->data;
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const struct spi_ambiq_config *cfg = dev->config;
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int ret;
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ret = am_hal_iom_initialize((cfg->base - REG_IOM_BASEADDR) / cfg->size, &data->IOMHandle);
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ret = cfg->pwr_func();
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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return ret;
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}
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#define AMBIQ_SPI_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static int pwr_on_ambiq_spi_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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k_busy_wait(PWRCTRL_MAX_WAIT_US); \
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return 0; \
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} \
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static struct spi_ambiq_data spi_ambiq_data##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_ambiq_data##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_ambiq_data##n, ctx)}; \
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static const struct spi_ambiq_config spi_ambiq_config##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.size = DT_INST_REG_SIZE(n), \
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.clock_freq = DT_INST_PROP(n, clock_frequency), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.pwr_func = pwr_on_ambiq_spi_##n}; \
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DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, NULL, &spi_ambiq_data##n, &spi_ambiq_config##n, \
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POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &spi_ambiq_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(AMBIQ_SPI_INIT)
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