102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/*
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* Copyright (c) 2024 Ambiq Micro Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <zephyr/drivers/interrupt_controller/gic.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/pm/pm.h>
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#include <zephyr/init.h>
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/* ambiq-sdk includes */
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#include <am_mcu_apollo.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(substate_id);
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__disable_irq();
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__set_BASEPRI(0);
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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/* Put ARM core to normal sleep. */
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am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_NORMAL);
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break;
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case PM_STATE_SUSPEND_TO_RAM:
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/* Put ARM core to deep sleep. */
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/* Cotex-m: power down, register value preserve.*/
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/* Cache: power down*/
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/* Flash: power down*/
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/* Sram: retention*/
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am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP);
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break;
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default:
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LOG_DBG("Unsupported power state %u", state);
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break;
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}
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}
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/**
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* @brief PM State Exit Post Operations
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*
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* For PM_STATE_SUSPEND_TO_IDLE:
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* Nothing is needed after soc woken up.
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*
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* For PM_STATE_SUSPEND_TO_RAM:
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* Flash, cache, sram automatically switch
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* to active state on wake up
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*
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* @param state PM State
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* @param substate_id Unused
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*
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*/
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(substate_id);
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__enable_irq();
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irq_unlock(0);
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}
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void ambiq_power_init(void)
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{
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am_hal_pwrctrl_mcu_memory_config_t sMcuMemCfg = {
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.eCacheCfg = AM_HAL_PWRCTRL_CACHE_NONE,
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.bRetainCache = true,
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.eDTCMCfg = AM_HAL_PWRCTRL_DTCM_384K,
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.eRetainDTCM = AM_HAL_PWRCTRL_DTCM_384K,
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.bEnableNVM0 = true,
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.bRetainNVM0 = false
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};
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am_hal_pwrctrl_sram_memcfg_t sSRAMCfg = {
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.eSRAMCfg = AM_HAL_PWRCTRL_SRAM_ALL,
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.eActiveWithMCU = AM_HAL_PWRCTRL_SRAM_NONE,
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.eActiveWithGFX = AM_HAL_PWRCTRL_SRAM_NONE,
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.eActiveWithDISP = AM_HAL_PWRCTRL_SRAM_NONE,
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.eActiveWithDSP = AM_HAL_PWRCTRL_SRAM_NONE,
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.eSRAMRetain = AM_HAL_PWRCTRL_SRAM_ALL
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};
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am_hal_pwrctrl_dsp_memory_config_t sDSPMemCfg = {
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.bEnableICache = false,
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.bRetainCache = false,
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.bEnableRAM = false,
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.bActiveRAM = false,
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.bRetainRAM = false
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};
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am_hal_pwrctrl_mcu_memory_config(&sMcuMemCfg);
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am_hal_pwrctrl_sram_config(&sSRAMCfg);
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am_hal_pwrctrl_dsp_memory_config(AM_HAL_DSP0, &sDSPMemCfg);
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am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_CRYPTO);
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}
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