78 lines
1.5 KiB
Plaintext
78 lines
1.5 KiB
Plaintext
/*
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* Copyright (c) 2020, Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#include "skeleton.dtsi"
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#define DT_FLASH_SIZE DT_SIZE_M(4)
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#define DT_SRAM_SIZE DT_SIZE_M(4)
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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intc: arcv2-intc {
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compatible = "snps,arcv2-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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timer0: timer0 {
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compatible = "snps,arc-timer";
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interrupts = <16 1>;
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interrupt-parent = <&intc>;
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};
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timer1: timer1 {
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compatible = "snps,arc-timer";
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interrupts = <17 1>;
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interrupt-parent = <&intc>;
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};
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/* We are carving out of DRAM for a pseudo flash and sram region */
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flash0: flash@80000000 {
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compatible = "soc-nv-flash";
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reg = <0x80000000 DT_FLASH_SIZE>;
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};
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sram0: sram@80400000 {
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device_type = "memory";
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reg = <0x80400000 DT_SRAM_SIZE>;
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};
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ns16550_uart0: uart@f0000000 {
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compatible = "ns16550";
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clock-frequency = <10000000>;
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reg = <0xf0000000 0x400>;
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current-speed = <115200>;
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interrupt-parent = <&intc>;
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interrupts = <24 1>;
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reg-shift = <2>;
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};
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ns16550_uart1: uart@f0002000 {
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compatible = "ns16550";
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clock-frequency = <10000000>;
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reg = <0xf0002000 0x400>;
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current-speed = <115200>;
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interrupt-parent = <&intc>;
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interrupts = <25 1>;
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reg-shift = <2>;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &ns16550_uart0;
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zephyr,shell-uart = &ns16550_uart0;
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zephyr,uart-pipe = &ns16550_uart1;
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};
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};
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