c276088567
Fixes #29915. Implements the memory layout and MPU configuration for Ethernet buffers for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are are reserved for this. The first 256 B are for the RX/TX descriptors and configured as strongly ordered, shareable memory. The rest is for RX/TX buffers and configured as non cacheable memory. This configuration is automatically applied for H7 chips if the SRAM3 memory is enabled in the device tree. Signed-off-by: Mario Jaun <mario.jaun@gmail.com> |
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| .. | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.dsa | ||
| Kconfig.e1000 | ||
| Kconfig.enc28j60 | ||
| Kconfig.enc424j600 | ||
| Kconfig.gecko | ||
| Kconfig.liteeth | ||
| Kconfig.mcux | ||
| Kconfig.native_posix | ||
| Kconfig.sam_gmac | ||
| Kconfig.smsc911x | ||
| Kconfig.stellaris | ||
| Kconfig.stm32_hal | ||
| Kconfig.w5500 | ||
| dsa_ksz8794.c | ||
| dsa_ksz8794.h | ||
| eth.h | ||
| eth_e1000.c | ||
| eth_e1000_priv.h | ||
| eth_enc28j60.c | ||
| eth_enc28j60_priv.h | ||
| eth_enc424j600.c | ||
| eth_enc424j600_priv.h | ||
| eth_gecko.c | ||
| eth_gecko_priv.h | ||
| eth_liteeth.c | ||
| eth_mcux.c | ||
| eth_native_posix.c | ||
| eth_native_posix_adapt.c | ||
| eth_native_posix_priv.h | ||
| eth_sam0_gmac.h | ||
| eth_sam_gmac.c | ||
| eth_sam_gmac_priv.h | ||
| eth_smsc911x.c | ||
| eth_smsc911x_priv.h | ||
| eth_stellaris.c | ||
| eth_stellaris_priv.h | ||
| eth_stm32_hal.c | ||
| eth_stm32_hal_priv.h | ||
| eth_w5500.c | ||
| eth_w5500_priv.h | ||
| phy_gecko.c | ||
| phy_gecko.h | ||
| phy_sam_gmac.c | ||
| phy_sam_gmac.h | ||