42 lines
1008 B
C
42 lines
1008 B
C
/*
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* Copyright 2022-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _NXP_S32_S32ZE_SOC_H_
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#define _NXP_S32_S32ZE_SOC_H_
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/* Do not let CMSIS to handle GIC */
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#define __GIC_PRESENT 0
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#if defined(CONFIG_SOC_S32Z270)
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#include <S32Z2.h>
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#else
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#error "SoC not supported"
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#endif
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#if defined(CONFIG_CMSIS_RTOS_V2)
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#include <cmsis_rtos_v2_adapt.h>
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#endif
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/* Aliases for peripheral base addresses */
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/* LINFlexD*/
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#define IP_LINFLEX_12_BASE IP_MSC_0_LIN_BASE
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/* NETC */
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#define IP_NETC_EMDIO_0_BASE IP_NETC__EMDIO_BASE_BASE
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/* MRU */
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#define IP_MRU_0_BASE IP_RTU0__MRU_0_BASE
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#define IP_MRU_1_BASE IP_RTU0__MRU_1_BASE
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#define IP_MRU_2_BASE IP_RTU0__MRU_2_BASE
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#define IP_MRU_3_BASE IP_RTU0__MRU_3_BASE
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#define IP_MRU_4_BASE IP_RTU1__MRU_0_BASE
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#define IP_MRU_5_BASE IP_RTU1__MRU_1_BASE
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#define IP_MRU_6_BASE IP_RTU1__MRU_2_BASE
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#define IP_MRU_7_BASE IP_RTU1__MRU_3_BASE
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#endif /* _NXP_S32_S32ZE_SOC_H_ */
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