51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <cmsis_core.h>
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#include <zephyr/sys/barrier.h>
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#include <OsIf.h>
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void soc_reset_hook(void)
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{
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/* enable peripheral port access at EL1 and EL0 */
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__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
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__asm__ volatile("orr r0, #1\n");
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__asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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/*
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* Take exceptions in Arm mode because Zephyr ASM code for Cortex-R Aarch32
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* is written for Arm
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*/
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__set_SCTLR(__get_SCTLR() & ~SCTLR_TE_Msk);
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if (IS_ENABLED(CONFIG_ICACHE)) {
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if (!(__get_SCTLR() & SCTLR_I_Msk)) {
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L1C_InvalidateICacheAll();
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__set_SCTLR(__get_SCTLR() | SCTLR_I_Msk);
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barrier_isync_fence_full();
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}
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}
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if (IS_ENABLED(CONFIG_DCACHE)) {
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if (!(__get_SCTLR() & SCTLR_C_Msk)) {
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L1C_InvalidateDCacheAll();
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__set_SCTLR(__get_SCTLR() | SCTLR_C_Msk);
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barrier_dsync_fence_full();
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}
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}
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}
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void soc_early_init_hook(void)
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{
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OsIf_Init(NULL);
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}
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