34 lines
714 B
C
34 lines
714 B
C
/*
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* Copyright (c) 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <errno.h>
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#include <zephyr/sys/sys_io.h>
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#include <adsp/cache.h>
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#ifndef __INC_IMX_SOC_H
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#define __INC_IMX_SOC_H
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/* Macros related to interrupt handling */
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#define XTENSA_IRQ_NUM_SHIFT 0
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#define XTENSA_IRQ_NUM_MASK 0xff
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/*
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* IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
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*
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* 1. Peripheral Register bit offset.
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*/
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#define XTENSA_IRQ_NUMBER(_irq) \
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((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
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extern void z_soc_irq_enable(uint32_t irq);
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extern void z_soc_irq_disable(uint32_t irq);
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extern int z_soc_irq_is_enabled(unsigned int irq);
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#endif /* __INC_IMX_SOC_H */
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