280 lines
6.9 KiB
C
280 lines
6.9 KiB
C
/*
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* Copyright (C) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_watchdog
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <soc/rtc_cntl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <soc.h>
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#include <string.h>
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#include <drivers/watchdog.h>
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#include <device.h>
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/* FIXME: This struct shall be removed from here, when esp32 timer driver got
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* implemented.
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* That's why the type name starts with `timer` not `wdt`
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*/
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struct timer_esp32_irq_regs_t {
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uint32_t *timer_int_ena;
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uint32_t *timer_int_clr;
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};
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struct wdt_esp32_regs_t {
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uint32_t config0;
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uint32_t config1;
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uint32_t config2;
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uint32_t config3;
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uint32_t config4;
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uint32_t config5;
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uint32_t feed;
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uint32_t wprotect;
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};
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enum wdt_mode {
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WDT_MODE_RESET = 0,
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WDT_MODE_INTERRUPT_RESET
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};
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struct wdt_esp32_data {
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uint32_t timeout;
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enum wdt_mode mode;
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wdt_callback_t callback;
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};
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struct wdt_esp32_config {
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void (*connect_irq)(void);
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const struct wdt_esp32_regs_t *base;
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const struct timer_esp32_irq_regs_t irq_regs;
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const struct {
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int source;
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int line;
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} irq;
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};
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#define DEV_CFG(dev) \
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((const struct wdt_esp32_config *const)(dev)->config_info)
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#define DEV_DATA(dev) \
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((struct wdt_esp32_data *)(dev)->driver_data)
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#define DEV_BASE(dev) \
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((volatile struct wdt_esp32_regs_t *)(DEV_CFG(dev))->base)
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/* ESP32 ignores writes to any register if WDTWPROTECT doesn't contain the
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* magic value of TIMG_WDT_WKEY_VALUE. The datasheet recommends unsealing,
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* making modifications, and sealing for every watchdog modification.
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*/
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static inline void wdt_esp32_seal(struct device *dev)
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{
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DEV_BASE(dev)->wprotect = 0U;
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}
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static inline void wdt_esp32_unseal(struct device *dev)
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{
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DEV_BASE(dev)->wprotect = TIMG_WDT_WKEY_VALUE;
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}
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static void wdt_esp32_enable(struct device *dev)
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{
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wdt_esp32_unseal(dev);
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DEV_BASE(dev)->config0 |= BIT(TIMG_WDT_EN_S);
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wdt_esp32_seal(dev);
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}
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static int wdt_esp32_disable(struct device *dev)
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{
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wdt_esp32_unseal(dev);
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DEV_BASE(dev)->config0 &= ~BIT(TIMG_WDT_EN_S);
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wdt_esp32_seal(dev);
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return 0;
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}
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static void adjust_timeout(struct device *dev, uint32_t timeout)
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{
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/* MWDT ticks every 12.5ns. Set the prescaler to 40000, so the
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* counter for each watchdog stage is decremented every 0.5ms.
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*/
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DEV_BASE(dev)->config1 = 40000U;
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DEV_BASE(dev)->config2 = timeout;
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DEV_BASE(dev)->config3 = timeout;
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}
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static void wdt_esp32_isr(struct device *dev);
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static int wdt_esp32_feed(struct device *dev, int channel_id)
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{
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wdt_esp32_unseal(dev);
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DEV_BASE(dev)->feed = 0xABAD1DEA; /* Writing any value to WDTFEED will reload it. */
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wdt_esp32_seal(dev);
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return 0;
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}
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static void set_interrupt_enabled(struct device *dev, bool setting)
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{
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*DEV_CFG(dev)->irq_regs.timer_int_clr |= TIMG_WDT_INT_CLR;
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if (setting) {
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*DEV_CFG(dev)->irq_regs.timer_int_ena |= TIMG_WDT_INT_ENA;
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irq_enable(DEV_CFG(dev)->irq.line);
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} else {
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*DEV_CFG(dev)->irq_regs.timer_int_ena &= ~TIMG_WDT_INT_ENA;
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irq_disable(DEV_CFG(dev)->irq.line);
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}
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}
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static int wdt_esp32_set_config(struct device *dev, uint8_t options)
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{
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struct wdt_esp32_data *data = DEV_DATA(dev);
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uint32_t v = DEV_BASE(dev)->config0;
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if (!data) {
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return -EINVAL;
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}
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/* Stages 3 and 4 are not used: disable them. */
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v |= TIMG_WDT_STG_SEL_OFF << TIMG_WDT_STG2_S;
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v |= TIMG_WDT_STG_SEL_OFF << TIMG_WDT_STG3_S;
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/* Wait for 3.2us before booting again. */
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v |= 7 << TIMG_WDT_SYS_RESET_LENGTH_S;
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v |= 7 << TIMG_WDT_CPU_RESET_LENGTH_S;
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if (data->mode == WDT_MODE_RESET) {
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/* Warm reset on timeout */
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v |= TIMG_WDT_STG_SEL_RESET_SYSTEM << TIMG_WDT_STG0_S;
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v |= TIMG_WDT_STG_SEL_OFF << TIMG_WDT_STG1_S;
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/* Disable interrupts for this mode. */
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v &= ~(TIMG_WDT_LEVEL_INT_EN | TIMG_WDT_EDGE_INT_EN);
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} else if (data->mode == WDT_MODE_INTERRUPT_RESET) {
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/* Interrupt first, and warm reset if not reloaded */
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v |= TIMG_WDT_STG_SEL_INT << TIMG_WDT_STG0_S;
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v |= TIMG_WDT_STG_SEL_RESET_SYSTEM << TIMG_WDT_STG1_S;
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/* Use level-triggered interrupts. */
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v |= TIMG_WDT_LEVEL_INT_EN;
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v &= ~TIMG_WDT_EDGE_INT_EN;
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} else {
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return -EINVAL;
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}
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wdt_esp32_unseal(dev);
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DEV_BASE(dev)->config0 = v;
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adjust_timeout(dev, data->timeout);
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set_interrupt_enabled(dev, data->mode == WDT_MODE_INTERRUPT_RESET);
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wdt_esp32_seal(dev);
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wdt_esp32_feed(dev, 0);
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return 0;
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}
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static int wdt_esp32_install_timeout(struct device *dev,
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const struct wdt_timeout_cfg *cfg)
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{
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struct wdt_esp32_data *data = DEV_DATA(dev);
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if (cfg->flags != WDT_FLAG_RESET_SOC) {
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return -ENOTSUP;
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}
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if (cfg->window.min != 0U || cfg->window.max == 0U) {
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return -EINVAL;
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}
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data->timeout = cfg->window.max;
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data->mode = (cfg->callback == NULL) ?
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WDT_MODE_RESET : WDT_MODE_INTERRUPT_RESET;
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data->callback = cfg->callback;
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return 0;
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}
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static int wdt_esp32_init(struct device *dev)
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{
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#ifdef CONFIG_WDT_DISABLE_AT_BOOT
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wdt_esp32_disable(dev);
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#endif
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/* This is a level 4 interrupt, which is handled by _Level4Vector,
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* located in xtensa_vectors.S.
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*/
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irq_disable(DEV_CFG(dev)->irq.line);
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DEV_CFG(dev)->connect_irq();
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wdt_esp32_enable(dev);
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return 0;
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}
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static const struct wdt_driver_api wdt_api = {
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.setup = wdt_esp32_set_config,
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.disable = wdt_esp32_disable,
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.install_timeout = wdt_esp32_install_timeout,
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.feed = wdt_esp32_feed
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};
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#define ESP32_WDT_INIT(idx) \
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DEVICE_DECLARE(wdt_esp32_##idx); \
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static void wdt_esp32_connect_irq_func##idx(void) \
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{ \
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esp32_rom_intr_matrix_set(0, ETS_TG##idx##_WDT_LEVEL_INTR_SOURCE, \
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CONFIG_WDT##idx##_ESP32_IRQ); \
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IRQ_CONNECT(CONFIG_WDT##idx##_ESP32_IRQ, \
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4, \
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wdt_esp32_isr, \
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DEVICE_GET(wdt_esp32_##idx), \
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0); \
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} \
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\
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static struct wdt_esp32_data wdt##idx##_data; \
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static struct wdt_esp32_config wdt_esp32_config##idx = { \
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.base = (struct wdt_esp32_regs_t *) DT_INST_REG_ADDR(idx), \
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.irq_regs = { \
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.timer_int_ena = (uint32_t *)TIMG_INT_ENA_TIMERS_REG(idx), \
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.timer_int_clr = (uint32_t *)TIMG_INT_CLR_TIMERS_REG(idx), \
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}, \
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.irq = { \
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.source = ETS_TG##idx##_WDT_LEVEL_INTR_SOURCE, \
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.line = CONFIG_WDT##idx##_ESP32_IRQ, \
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}, \
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.connect_irq = wdt_esp32_connect_irq_func##idx \
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}; \
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\
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DEVICE_AND_API_INIT(wdt_esp32_##idx, DT_INST_LABEL(idx), \
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wdt_esp32_init, \
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&wdt##idx##_data, \
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&wdt_esp32_config##idx, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&wdt_api)
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static void wdt_esp32_isr(struct device *dev)
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{
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struct wdt_esp32_data *data = DEV_DATA(dev);
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if (data->callback) {
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data->callback(dev, 0);
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}
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*DEV_CFG(dev)->irq_regs.timer_int_clr |= TIMG_WDT_INT_CLR;
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}
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(wdt0), okay)
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ESP32_WDT_INIT(0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(wdt1), okay)
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ESP32_WDT_INIT(1);
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#endif
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