121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_DMA_DMA_DW_H_
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#define ZEPHYR_DRIVERS_DMA_DMA_DW_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DW_CTLL_INT_EN (1 << 0)
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#define DW_CTLL_DST_WIDTH(x) (x << 1)
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#define DW_CTLL_SRC_WIDTH(x) (x << 4)
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#define DW_CTLL_DST_INC (0 << 8)
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#define DW_CTLL_DST_FIX (1 << 8)
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#define DW_CTLL_SRC_INC (0 << 10)
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#define DW_CTLL_SRC_FIX (1 << 10)
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#define DW_CTLL_DST_MSIZE(x) (x << 11)
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#define DW_CTLL_SRC_MSIZE(x) (x << 14)
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#define DW_CTLL_FC(x) (x << 20)
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#define DW_CTLL_FC_M2M (0 << 20)
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#define DW_CTLL_FC_M2P (1 << 20)
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#define DW_CTLL_FC_P2M (2 << 20)
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#define DW_CTLL_FC_P2P (3 << 20)
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#define DW_CTLL_LLP_D_EN (1 << 27)
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#define DW_CTLL_LLP_S_EN (1 << 28)
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/* data for each DMA channel */
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struct dma_chan_data {
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uint32_t direction;
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void *blkcallback_arg;
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void (*dma_blkcallback)(void *arg, uint32_t channel,
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int error_code);
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void *tfrcallback_arg;
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void (*dma_tfrcallback)(void *arg, uint32_t channel,
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int error_code);
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};
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#define DW_MAX_CHAN 8
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#define DW_CH_SIZE 0x58
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#define BYT_CHAN_OFFSET(chan) (DW_CH_SIZE * chan)
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#define DW_SAR(chan) \
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(0x0000 + BYT_CHAN_OFFSET(chan))
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#define DW_DAR(chan) \
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(0x0008 + BYT_CHAN_OFFSET(chan))
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#define DW_LLP(chan) \
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(0x0010 + BYT_CHAN_OFFSET(chan))
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#define DW_CTRL_LOW(chan) \
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(0x0018 + BYT_CHAN_OFFSET(chan))
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#define DW_CTRL_HIGH(chan) \
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(0x001C + BYT_CHAN_OFFSET(chan))
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#define DW_CFG_LOW(chan) \
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(0x0040 + BYT_CHAN_OFFSET(chan))
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#define DW_CFG_HIGH(chan) \
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(0x0044 + BYT_CHAN_OFFSET(chan))
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/* registers */
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#define DW_RAW_TFR 0x02C0
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#define DW_RAW_BLOCK 0x02C8
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#define DW_RAW_SRC_TRAN 0x02D0
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#define DW_RAW_DST_TRAN 0x02D8
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#define DW_RAW_ERR 0x02E0
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#define DW_STATUS_TFR 0x02E8
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#define DW_STATUS_BLOCK 0x02F0
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#define DW_STATUS_SRC_TRAN 0x02F8
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#define DW_STATUS_DST_TRAN 0x0300
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#define DW_STATUS_ERR 0x0308
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#define DW_MASK_TFR 0x0310
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#define DW_MASK_BLOCK 0x0318
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#define DW_MASK_SRC_TRAN 0x0320
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#define DW_MASK_DST_TRAN 0x0328
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#define DW_MASK_ERR 0x0330
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#define DW_CLEAR_TFR 0x0338
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#define DW_CLEAR_BLOCK 0x0340
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#define DW_CLEAR_SRC_TRAN 0x0348
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#define DW_CLEAR_DST_TRAN 0x0350
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#define DW_CLEAR_ERR 0x0358
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#define DW_INTR_STATUS 0x0360
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#define DW_DMA_CFG 0x0398
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#define DW_DMA_CHAN_EN 0x03A0
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/* channel bits */
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#define INT_MASK(chan) (0x100 << chan)
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#define INT_UNMASK(chan) (0x101 << chan)
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#define INT_MASK_ALL 0xFF00
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#define INT_UNMASK_ALL 0xFFFF
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#define CHAN_ENABLE(chan) (0x101 << chan)
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#define CHAN_DISABLE(chan) (0x100 << chan)
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/* TODO: add FIFO sizes */
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struct chan_arbit_data {
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uint16_t class;
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uint16_t weight;
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};
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struct dw_drv_plat_data {
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struct chan_arbit_data chan[DW_MAX_CHAN];
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};
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/* Device run time data */
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struct dw_dma_dev_data {
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struct dw_drv_plat_data *channel_data;
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struct dma_chan_data chan[DW_MAX_CHAN];
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};
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/* Device constant configuration parameters */
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struct dw_dma_dev_cfg {
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uint32_t base;
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void (*irq_config)(void);
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_DMA_DMA_DW_H_ */
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