54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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#include <soc/dport_reg.h>
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#include <soc/rtc_cntl_reg.h>
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#include <esp32/rom/ets_sys.h>
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#include <esp32/rom/spi_flash.h>
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#include <zephyr/types.h>
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#include <stdbool.h>
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#include <arch/xtensa/arch.h>
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static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
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{
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sys_write32(sys_read32(mem_addr) | v, mem_addr);
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}
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static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
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{
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sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
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}
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extern void esp32_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
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extern int esp32_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
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bool inverted);
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extern int esp32_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
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bool out_inverted,
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bool out_enabled_inverted);
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extern void esp32_rom_uart_attach(void);
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extern void esp32_rom_uart_tx_wait_idle(uint8_t uart_no);
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extern STATUS esp32_rom_uart_tx_one_char(uint8_t chr);
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extern STATUS esp32_rom_uart_rx_one_char(uint8_t *chr);
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extern void esp32_rom_Cache_Flush(int cpu);
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extern void esp32_rom_Cache_Read_Enable(int cpu);
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extern void esp32_rom_ets_set_appcpu_boot_addr(void *addr);
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/* ROM functions which read/write internal i2c control bus for PLL, APLL */
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extern uint8_t esp32_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
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extern void esp32_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
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/* ROM information related to SPI Flash chip timing and device */
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extern esp_rom_spiflash_chip_t g_rom_flashchip;
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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#endif /* __SOC_H__ */
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