zephyr/soc/riscv/openisa_rv32m1
Daniel Leung 8a79ce1428 riscv: add support for thread local storage
Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-10-24 10:52:00 -07:00
..
CMakeLists.txt
Kconfig
Kconfig.defconfig
Kconfig.soc
linker.ld
soc.c
soc.h
soc_context.h
soc_irq.S
soc_offsets.h
soc_ri5cy.h
soc_zero_riscy.h
vector.S
vector_table.ld
wdog.S