272 lines
6.3 KiB
C
272 lines
6.3 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <pwm.h>
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#include <device.h>
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#include <kernel.h>
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#include <init.h>
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#include <power.h>
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#include <misc/util.h>
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#include "qm_pwm.h"
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#include "clk.h"
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#define HW_CLOCK_CYCLES_PER_USEC (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / \
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USEC_PER_SEC)
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/* pwm uses 32 bits counter to control low and high period */
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#define MAX_LOW_PERIOD_IN_HW_CLOCK_CYCLES (((u64_t)1) << 32)
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#define MAX_HIGH_PERIOD_IN_HW_CLOCK_CYCLES (((u64_t)1) << 32)
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#define MAX_PERIOD_IN_HW_CLOCK_CYCLES (MAX_LOW_PERIOD_IN_HW_CLOCK_CYCLES + \
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MAX_HIGH_PERIOD_IN_HW_CLOCK_CYCLES)
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/* in micro seconds. */
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#define MAX_PERIOD (MAX_PERIOD_IN_HW_CLOCK_CYCLES / HW_CLOCK_CYCLES_PER_USEC)
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/**
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* in micro seconds. To be able to get 1% granularity, MIN_PERIOD should
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* have at least 100 HW clock cycles.
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*/
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#define MIN_PERIOD ((100 + (HW_CLOCK_CYCLES_PER_USEC - 1)) / \
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HW_CLOCK_CYCLES_PER_USEC)
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/* in micro seconds */
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#define DEFAULT_PERIOD 2000
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struct pwm_data {
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#ifdef CONFIG_PWM_QMSI_API_REENTRANCY
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struct k_sem sem;
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#endif
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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u32_t device_power_state;
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#endif
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u32_t channel_period[CONFIG_PWM_QMSI_NUM_PORTS];
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};
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static struct pwm_data pwm_context;
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#ifdef CONFIG_PWM_QMSI_API_REENTRANCY
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#define RP_GET(dev) (&((struct pwm_data *)(dev->driver_data))->sem)
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#else
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#define RP_GET(dev) (NULL)
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#endif
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static int __set_one_port(struct device *dev, qm_pwm_t id, u32_t pwm,
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u32_t on, u32_t off)
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{
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qm_pwm_config_t cfg;
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int ret_val = 0;
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if (IS_ENABLED(CONFIG_PWM_QMSI_API_REENTRANCY)) {
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k_sem_take(RP_GET(dev), K_FOREVER);
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}
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/* Disable timer to prevent any output */
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qm_pwm_stop(id, pwm);
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if (on == 0) {
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/* stop PWM if so specified */
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goto pwm_set_port_return;
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}
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/**
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* off period must be more than zero. Otherwise, the PWM pin will be
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* turned off. Let's use the minimum value which is 1 for this case.
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*/
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if (off == 0) {
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off = 1;
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}
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/* PWM mode, user-defined count mode, timer disabled */
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cfg.mode = QM_PWM_MODE_PWM;
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/* No interrupts */
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cfg.mask_interrupt = true;
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cfg.callback = NULL;
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cfg.callback_data = NULL;
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/* Data for the timer to stay high and low */
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cfg.hi_count = on;
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cfg.lo_count = off;
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if (qm_pwm_set_config(id, pwm, &cfg) != 0) {
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ret_val = -EIO;
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goto pwm_set_port_return;
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}
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/* Enable timer so it starts running and counting */
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qm_pwm_start(id, pwm);
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pwm_set_port_return:
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if (IS_ENABLED(CONFIG_PWM_QMSI_API_REENTRANCY)) {
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k_sem_give(RP_GET(dev));
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}
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return ret_val;
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}
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/*
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* Set the period and pulse width for a PWM pin.
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*
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* For example, with a nominal system clock of 32MHz, each count represents
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* 31.25ns (e.g. period = 100 means the pulse is to repeat every 3125ns). The
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* duration of one count depends on system clock. Refer to the hardware manual
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* for more information.
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*
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* Parameters
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* dev: Pointer to PWM device structure
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* pwm: PWM port number to set
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* period_cycles: Period (in timer count)
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* pulse_cycles: Pulse width (in timer count).
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*
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* return 0, or negative errno code
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*/
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static int pwm_qmsi_pin_set(struct device *dev, u32_t pwm,
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u32_t period_cycles, u32_t pulse_cycles)
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{
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u32_t high, low;
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if (pwm >= CONFIG_PWM_QMSI_NUM_PORTS) {
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return -EINVAL;
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}
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if (period_cycles == 0 || pulse_cycles > period_cycles) {
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return -EINVAL;
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}
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high = pulse_cycles;
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low = period_cycles - pulse_cycles;
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/*
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* low must be more than zero. Otherwise, the PWM pin will be
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* turned off. Let's make sure low is always more than zero.
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*/
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if (low == 0) {
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high--;
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low = 1;
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}
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return __set_one_port(dev, QM_PWM_0, pwm, high, low);
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}
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/*
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* Get the clock rate (cycles per second) for a PWM pin.
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*
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* Parameters
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* dev: Pointer to PWM device structure
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* pwm: PWM port number
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* cycles: Pointer to the memory to store clock rate (cycles per second)
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*
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* return 0, or negative errno code
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*/
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static int pwm_qmsi_get_cycles_per_sec(struct device *dev, u32_t pwm,
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u64_t *cycles)
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{
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if (cycles == NULL) {
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return -EINVAL;
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}
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*cycles = (u64_t)clk_sys_get_ticks_per_us() * USEC_PER_SEC;
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return 0;
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}
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static const struct pwm_driver_api pwm_qmsi_drv_api_funcs = {
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.pin_set = pwm_qmsi_pin_set,
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.get_cycles_per_sec = pwm_qmsi_get_cycles_per_sec,
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static void pwm_qmsi_set_power_state(struct device *dev, u32_t power_state)
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{
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struct pwm_data *context = dev->driver_data;
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context->device_power_state = power_state;
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}
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#else
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#define pwm_qmsi_set_power_state(...)
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#endif
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static int pwm_qmsi_init(struct device *dev)
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{
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struct pwm_data *context = dev->driver_data;
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u32_t *channel_period = context->channel_period;
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for (int i = 0; i < CONFIG_PWM_QMSI_NUM_PORTS; i++) {
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channel_period[i] = DEFAULT_PERIOD *
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HW_CLOCK_CYCLES_PER_USEC;
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}
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clk_periph_enable(CLK_PERIPH_PWM_REGISTER | CLK_PERIPH_CLK);
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if (IS_ENABLED(CONFIG_PWM_QMSI_API_REENTRANCY)) {
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k_sem_init(RP_GET(dev), 0, UINT_MAX);
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k_sem_give(RP_GET(dev));
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}
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pwm_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static qm_pwm_context_t pwm_ctx;
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static u32_t pwm_qmsi_get_power_state(struct device *dev)
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{
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struct pwm_data *context = dev->driver_data;
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return context->device_power_state;
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}
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static int pwm_qmsi_suspend(struct device *dev)
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{
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qm_pwm_save_context(QM_PWM_0, &pwm_ctx);
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pwm_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
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return 0;
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}
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static int pwm_qmsi_resume_from_suspend(struct device *dev)
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{
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qm_pwm_restore_context(QM_PWM_0, &pwm_ctx);
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pwm_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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/*
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* Implements the driver control management functionality
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* the *context may include IN data or/and OUT data
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*/
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static int pwm_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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return pwm_qmsi_suspend(dev);
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} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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return pwm_qmsi_resume_from_suspend(dev);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((u32_t *)context) = pwm_qmsi_get_power_state(dev);
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return 0;
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}
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return 0;
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}
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#endif
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DEVICE_DEFINE(pwm_qmsi_0, CONFIG_PWM_QMSI_DEV_NAME, pwm_qmsi_init,
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pwm_qmsi_device_ctrl, &pwm_context, NULL,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&pwm_qmsi_drv_api_funcs);
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