145 lines
3.7 KiB
C
145 lines
3.7 KiB
C
/* Copyright(c) 2021 Intel Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <zephyr/devicetree.h>
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#include <soc_util.h>
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#include <zephyr/cache.h>
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#include <adsp_shim.h>
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#include <adsp_memory.h>
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#include <cpu_init.h>
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#include "manifest.h"
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#define DELAY_COUNT 256
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#define LPSRAM_MASK(x) 0x00000003
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#define PLATFORM_INIT_HPSRAM
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#define PLATFORM_INIT_LPSRAM
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BUILD_ASSERT((DT_REG_SIZE(DT_NODELABEL(sram0)) % SRAM_BANK_SIZE) == 0,
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"sram0 must be divisible by 64*1024 bank size.");
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/*
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* Function powers up a number of memory banks provided as an argument
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* and gates remaining memory banks
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*/
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static __imr void hp_sram_pm_banks(uint32_t banks)
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{
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#ifdef CONFIG_ADSP_INIT_HPSRAM
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uint32_t status, ebb_mask0, ebb_mask1, ebb_avail_mask0, ebb_avail_mask1,
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total_banks_count = HPSRAM_EBB_COUNT;
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CAVS_SHIM.ldoctl = SHIM_LDOCTL_HPSRAM_LDO_ON;
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/* Add some delay before touch power register */
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z_idelay(DELAY_COUNT);
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/*
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* bit masks reflect total number of available EBB (banks) in each
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* segment; current implementation supports 2 segments 0,1
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*/
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if (total_banks_count > EBB_SEG_SIZE) {
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ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEG_SIZE - 1, 0);
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ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count -
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EBB_SEG_SIZE - 1, 0);
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} else {
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ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1, 0);
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ebb_avail_mask1 = 0;
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}
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/* bit masks of banks that have to be powered up in each segment */
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if (banks > EBB_SEG_SIZE) {
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ebb_mask0 = (uint32_t)GENMASK(EBB_SEG_SIZE - 1, 0);
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ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEG_SIZE - 1,
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0);
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} else {
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/* assumption that ebb_in_use is > 0 */
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ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0);
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ebb_mask1 = 0;
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}
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/* HSPGCTL, HSRMCTL use reverse logic - 0 means EBB is power gated */
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CAVS_L2LM.hspgctl0 = (~ebb_mask0) & ebb_avail_mask0;
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CAVS_L2LM.hsrmctl0 = (~ebb_mask0) & ebb_avail_mask0;
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CAVS_L2LM.hspgctl1 = (~ebb_mask1) & ebb_avail_mask1;
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CAVS_L2LM.hsrmctl1 = (~ebb_mask1) & ebb_avail_mask1;
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/*
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* Query the power status of first part of HP memory
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* to check whether it has been powered up. A few
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* cycles are needed for it to be powered up
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*/
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status = CAVS_L2LM.hspgists0;
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while (status != ((~ebb_mask0) & ebb_avail_mask0)) {
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z_idelay(DELAY_COUNT);
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status = CAVS_L2LM.hspgists0;
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}
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/*
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* Query the power status of second part of HP memory
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* and do as above code
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*/
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status = CAVS_L2LM.hspgists1;
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while (status != ((~ebb_mask1) & ebb_avail_mask1)) {
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z_idelay(DELAY_COUNT);
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status = CAVS_L2LM.hspgists1;
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}
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/* Add some delay before touch power register */
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z_idelay(DELAY_COUNT);
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CAVS_SHIM.ldoctl = SHIM_LDOCTL_HPSRAM_LDO_BYPASS;
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#endif
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}
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__imr void hp_sram_init(uint32_t memory_size)
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{
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uint32_t ebb_in_use;
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/*
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* Calculate total number of used SRAM banks (EBB)
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* to power up only necessary banks
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*/
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ebb_in_use = DIV_ROUND_UP(memory_size, SRAM_BANK_SIZE);
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hp_sram_pm_banks(ebb_in_use);
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bbzero((void *)L2_SRAM_BASE, L2_SRAM_SIZE);
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}
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__imr void lp_sram_init(void)
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{
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#ifdef PLATFORM_INIT_LPSRAM
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uint32_t timeout_counter;
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timeout_counter = DELAY_COUNT;
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CAVS_SHIM.ldoctl = SHIM_LDOCTL_LPSRAM_LDO_ON;
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/* Add some delay before writing power registers */
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z_idelay(DELAY_COUNT);
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/* FIXME */
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CAVS_L2LM.lspgctl = CAVS_L2LM.lspgists & ~LPSRAM_MASK(0);
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/* Add some delay before checking the status */
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z_idelay(DELAY_COUNT);
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/*
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* Query the power status of first part of LP memory
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* to check whether it has been powered up. A few
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* cycles are needed for it to be powered up
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*/
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/* FIXME */
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while (CAVS_L2LM.lspgists && timeout_counter--) {
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z_idelay(DELAY_COUNT);
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}
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CAVS_SHIM.ldoctl = SHIM_LDOCTL_LPSRAM_LDO_BYPASS;
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bbzero((void *)LP_SRAM_BASE, LP_SRAM_SIZE);
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#endif
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}
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