264 lines
7.6 KiB
C
264 lines
7.6 KiB
C
/*
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* Copyright (c) 2024 GARDENA GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT silabs_si32_gpio
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/kernel.h>
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#include <SI32_PBCFG_A_Type.h>
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#include <SI32_PBSTD_A_Type.h>
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#include <si32_device.h>
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#include <errno.h>
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struct gpio_si32_config {
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struct gpio_driver_config common;
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SI32_PBSTD_A_Type *base;
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bool disable_pullups;
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};
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struct gpio_si32_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t cb;
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gpio_port_pins_t trig_low;
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gpio_port_pins_t trig_high;
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uint32_t pin_values;
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};
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static int gpio_si32_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_si32_config *config = dev->config;
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uint32_t key = irq_lock();
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/* Simultaneous input & output mode not supported */
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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SI32_PBSTD_A_write_pins_high(config->base, BIT(pin));
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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SI32_PBSTD_A_write_pins_low(config->base, BIT(pin));
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}
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SI32_PBSTD_A_set_pins_push_pull_output(config->base, BIT(pin));
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} else if (flags & GPIO_INPUT) {
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SI32_PBSTD_A_set_pins_digital_input(config->base, BIT(pin));
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} else {
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SI32_PBSTD_A_set_pins_analog(config->base, BIT(pin));
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}
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/* Initially, configure interrupt to trigger on the active value.
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* Otherwise we'd get an interrupt immediately after enabling them.
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*/
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if (flags & GPIO_ACTIVE_HIGH) {
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config->base->PM_SET = BIT(pin);
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} else {
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config->base->PM_CLR = BIT(pin);
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}
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irq_unlock(key);
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return 0;
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}
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static int gpio_si32_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_si32_config *config = dev->config;
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*value = SI32_PBSTD_A_read_pins(config->base);
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return 0;
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}
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static int gpio_si32_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_si32_config *config = dev->config;
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SI32_PBSTD_A_write_pins_masked(config->base, value, mask);
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return 0;
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}
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static int gpio_si32_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_si32_config *config = dev->config;
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SI32_PBSTD_A_write_pins_high(config->base, pins);
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return 0;
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}
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static int gpio_si32_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_si32_config *config = dev->config;
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SI32_PBSTD_A_write_pins_low(config->base, pins);
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return 0;
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}
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static int gpio_si32_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_si32_config *config = dev->config;
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SI32_PBSTD_A_toggle_pins(config->base, pins);
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return 0;
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}
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static int gpio_si32_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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const struct gpio_si32_config *config = dev->config;
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struct gpio_si32_data *data = dev->data;
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int ret;
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const uint32_t key = irq_lock();
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if (mode == GPIO_INT_MODE_DISABLED) {
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config->base->PMEN_CLR = BIT(pin);
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WRITE_BIT(data->trig_low, pin, 0);
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WRITE_BIT(data->trig_high, pin, 0);
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ret = 0;
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goto unlock;
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} else if (mode == GPIO_INT_MODE_EDGE) {
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} else {
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/* Not yet implemented */
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ret = -ENOTSUP;
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goto unlock;
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}
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WRITE_BIT(data->trig_low, pin, trig & GPIO_INT_TRIG_LOW);
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WRITE_BIT(data->trig_high, pin, trig & GPIO_INT_TRIG_HIGH);
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config->base->PMEN_SET = BIT(pin);
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ret = 0;
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unlock:
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irq_unlock(key);
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return ret;
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}
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static int gpio_si32_manage_callback(const struct device *dev, struct gpio_callback *callback,
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bool set)
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{
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struct gpio_si32_data *data = dev->data;
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static const struct gpio_driver_api gpio_si32_driver = {
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.pin_configure = gpio_si32_configure,
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.port_get_raw = gpio_si32_port_get_raw,
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.port_set_masked_raw = gpio_si32_port_set_masked_raw,
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.port_set_bits_raw = gpio_si32_port_set_bits_raw,
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.port_clear_bits_raw = gpio_si32_port_clear_bits_raw,
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.port_toggle_bits = gpio_si32_port_toggle_bits,
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.pin_interrupt_configure = gpio_si32_pin_interrupt_configure,
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.manage_callback = gpio_si32_manage_callback,
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};
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static int gpio_si32_init(const struct device *dev)
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{
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const struct gpio_si32_config *config = dev->config;
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if (config->disable_pullups) {
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SI32_PBSTD_A_disable_pullup_resistors(config->base);
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}
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return 0;
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}
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#define GPIO_DEVICE_INIT(inst) \
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static const struct gpio_si32_config gpio_si32_cfg_##inst = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
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}, \
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.base = (SI32_PBSTD_A_Type *)DT_INST_REG_ADDR(inst), \
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.disable_pullups = DT_INST_PROP(inst, disable_pullups), \
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}; \
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static struct gpio_si32_data gpio_si32_data_##inst; \
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DEVICE_DT_INST_DEFINE(inst, gpio_si32_init, NULL, &gpio_si32_data_##inst, \
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&gpio_si32_cfg_##inst, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_si32_driver);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_DEVICE_INIT)
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#define GPIO_DEVICE_LIST_ENTRY(inst) DEVICE_DT_GET(DT_DRV_INST(inst)),
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static const struct device *gpio_devices[] = {DT_INST_FOREACH_STATUS_OKAY(GPIO_DEVICE_LIST_ENTRY)};
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/* The hardware only supports level interrupts, so we have to emulate edge
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* interrupts in this handler.
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*/
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static void gpio_si32_irq_handler(const struct device *arg)
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{
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ARG_UNUSED(arg);
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irq_disable(PMATCH_IRQn);
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NVIC_ClearPendingIRQ(PMATCH_IRQn);
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for (size_t i = 0; i < ARRAY_SIZE(gpio_devices); i++) {
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const struct device *dev = gpio_devices[i];
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const struct gpio_si32_config *config = dev->config;
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struct gpio_si32_data *data = dev->data;
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const uint32_t pmen = SI32_PBSTD_A_read_pmen(config->base);
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const uint32_t pm = SI32_PBSTD_A_read_pm(config->base);
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const uint32_t values = SI32_PBSTD_A_read_pins(config->base);
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/* Invert triggers for all pins which are at their trigger
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* values. This disables interrupts until they change again
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* since the hardware only supports level interrupts.
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*/
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const uint32_t pins_not_at_trigger_value = (pm ^ values) & pmen;
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const uint32_t pins_at_trigger_value = (~pins_not_at_trigger_value) & pmen;
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SI32_PBSTD_A_write_pm(config->base, pm ^ pins_at_trigger_value);
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/* To check which pins actually changed we have to store and
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* compare the previous value.
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*/
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const uint32_t changed_pins = (values ^ data->pin_values) & pmen;
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data->pin_values = values;
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if (changed_pins) {
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/* The user might be interested in both levels or just one,
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* so filter those events here.
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*/
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const uint32_t changed_pins_high =
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(values & changed_pins) & data->trig_high;
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const uint32_t changed_pins_low =
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((~values) & changed_pins) & data->trig_low;
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gpio_fire_callbacks(&data->cb, dev, changed_pins_high | changed_pins_low);
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}
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}
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irq_enable(PMATCH_IRQn);
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}
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static int gpio_si32_common_init(void)
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{
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/* This is the only mode we support right now */
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SI32_PBCFG_A_select_port_match_mode_pin_match(SI32_PBCFG_0);
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IRQ_CONNECT(PMATCH_IRQn, 0, gpio_si32_irq_handler, NULL, 0);
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irq_enable(PMATCH_IRQn);
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return 0;
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}
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SYS_INIT(gpio_si32_common_init, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY);
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