80 lines
1.8 KiB
C
80 lines
1.8 KiB
C
/*
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_BENCHMARK_CMSIS_DSP_COMMON_BENCHMARK_COMMON_H_
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#define ZEPHYR_BENCHMARK_CMSIS_DSP_COMMON_BENCHMARK_COMMON_H_
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#include <ztest.h>
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#include <zephyr.h>
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#if defined(CONFIG_CPU_CORTEX_M_HAS_DWT)
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/* Use cycle counting on the Cortex-M devices that support DWT */
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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static ALWAYS_INLINE void benchmark_begin(uint32_t *irq_key, uint32_t *timestamp)
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{
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ARG_UNUSED(timestamp);
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/* Lock interrupts to prevent preemption */
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*irq_key = irq_lock();
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/* Start DWT cycle counter */
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DWT->CYCCNT = 0;
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
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}
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static ALWAYS_INLINE uint32_t benchmark_end(uint32_t irq_key, uint32_t timestamp)
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{
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/* Stop DWT cycle counter */
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DWT->CTRL &= ~DWT_CTRL_CYCCNTENA_Msk;
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/* Unlock interrupts */
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irq_unlock(irq_key);
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/* Return DWT cycle counter value */
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return DWT->CYCCNT;
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}
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#define BENCHMARK_TYPE "Processor Cycles"
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#else
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/* Use system timer clock on other systems */
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static ALWAYS_INLINE void benchmark_begin(uint32_t *irq_key, uint32_t *timestamp)
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{
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volatile uint32_t now;
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/* Lock interrupts to prevent preemption */
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*irq_key = irq_lock();
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/* Read timestamp for the beginning of benchmark */
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now = k_cycle_get_32();
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/* Store timestamp */
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*timestamp = now;
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}
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static ALWAYS_INLINE uint32_t benchmark_end(uint32_t irq_key, uint32_t timestamp)
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{
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volatile uint32_t now;
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/* Read timestamp for the end of benchmark */
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now = k_cycle_get_32();
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/* Unlock interrupts */
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irq_unlock(irq_key);
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/* Return timespan between the beginning and the end of benchmark */
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return now - timestamp;
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}
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#define BENCHMARK_TYPE "System Timer Cycles"
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#endif
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#endif /* ZEPHYR_BENCHMARK_CMSIS_DSP_COMMON_BENCHMARK_COMMON_H_ */
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