350 lines
9.5 KiB
C
350 lines
9.5 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __QM_ISR_H__
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#define __QM_ISR_H__
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#include "qm_common.h"
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#include "qm_soc_regs.h"
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/**
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* Interrupt Service Routines.
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*
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* @defgroup groupISR ISR
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* @{
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*/
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#if (QUARK_D2000)
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/**
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* ISR for ADC 0 convert and calibration interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_ADC_0_CAL_INT, qm_adc_0_cal_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_adc_0_cal_isr);
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/**
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* ISR for ADC 0 change mode interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_ADC_0_PWR_INT, qm_adc_0_pwr_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_adc_0_pwr_isr);
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#endif /* QUARK_D2000 */
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/**
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* ISR for Always-on Periodic Timer 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_AONPT_0_INT, qm_aonpt_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_aonpt_0_isr);
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/**
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* ISR for Analog Comparator 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_COMPARATOR_0_INT, qm_comparator_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_comparator_0_isr);
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/**
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* ISR for DMA error interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_ERROR_INT, qm_dma_0_error_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_error_isr);
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/**
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* ISR for DMA channel 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_INT_0, qm_dma_0_isr_0);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_isr_0);
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/**
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* ISR for DMA channel 1 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_INT_1, qm_dma_0_isr_1);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_isr_1);
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#if (QUARK_SE)
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/**
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* ISR for DMA channel 2 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_INT_2, qm_dma_0_isr_2);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_isr_2);
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/**
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* ISR for DMA channel 3 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_INT_3, qm_dma_0_isr_3);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_isr_3);
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/**
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* ISR for DMA channel 4 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_INT_4, qm_dma_0_isr_4);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_isr_4);
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/**
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* ISR for DMA channel 5 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_INT_5, qm_dma_0_isr_5);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_isr_5);
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/**
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* ISR for DMA channel 6 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_INT_6, qm_dma_0_isr_6);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_isr_6);
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/**
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* ISR for DMA 0 channel 7 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_DMA_0_INT_7, qm_dma_0_isr_7);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_dma_0_isr_7);
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#endif /* QUARK_SE */
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/**
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* ISR for FPR 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_FLASH_MPR_0_INT, qm_flash_mpr_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_flash_mpr_0_isr);
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/**
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* ISR for FPR 1 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_FLASH_MPR_1_INT, qm_flash_mpr_1_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_flash_mpr_1_isr);
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/**
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* ISR for GPIO 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_GPIO_0_INT, qm_gpio_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_gpio_0_isr);
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#if (HAS_AON_GPIO)
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/**
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* ISR for AON GPIO 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_AON_GPIO_0_INT, qm_aon_gpio_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_aon_gpio_0_isr);
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#endif /* HAS_AON_GPIO */
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/**
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* ISR for I2C 0 irq mode transfer interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_I2C_0_INT, qm_i2c_0_irq_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_i2c_0_irq_isr);
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/**
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* ISR for I2C 1 irq mode transfer interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_I2C_1_INT, qm_i2c_1_irq_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_i2c_1_irq_isr);
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/**
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* ISR for I2C 0 dma mode transfer interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_I2C_0_INT, qm_i2c_0_dma_isr);
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* @endcode if DMA based transfers are used.
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*/
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QM_ISR_DECLARE(qm_i2c_0_dma_isr);
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/**
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* ISR for I2C 1 dma mode transfer interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_I2C_1_INT, qm_i2c_1_dma_isr);
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* @endcode if DMA based transfers are used.
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*/
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QM_ISR_DECLARE(qm_i2c_1_dma_isr);
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/**
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* ISR for Mailbox interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_MAILBOX_0_INT, qm_mailbox_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_mailbox_0_isr);
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/**
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* ISR for Memory Protection Region interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_SRAM_MPR_0_INT, qm_sram_mpr_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_sram_mpr_0_isr);
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/**
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* ISR for PIC Timer interrupt.
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*
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* On Quark Microcontroller D2000 Development Platform,
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* this function needs to be registered with:
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* @code qm_int_vector_request(QM_X86_PIC_TIMER_INT_VECTOR,
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* qm_pic_timer_0_isr);
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* @endcode if IRQ based transfers are used.
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*
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* On Quark SE, this function needs to be registered with:
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* @code qm_irq_request(QM_IRQ_PIC_TIMER, qm_pic_timer_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_pic_timer_0_isr);
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/**
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* ISR for PWM 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_PWM_0_INT, qm_pwm_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_pwm_0_isr);
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/**
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* ISR for RTC 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_RTC_0_INT, qm_rtc_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_rtc_0_isr);
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/**
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* ISR for SPI Master 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_SPI_MASTER_0_INT, qm_spi_master_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_spi_master_0_isr);
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#if (QUARK_SE)
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/**
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* ISR for SPI Master 1 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_SPI_MASTER_1_INT, qm_spi_master_1_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_spi_master_1_isr);
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#endif /* QUARK_SE */
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/**
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* ISR for UART 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_UART_0_INT, qm_uart_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_uart_0_isr);
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/**
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* ISR for UART 1 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_UART_1_INT, qm_uart_1_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_uart_1_isr);
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/**
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* ISR for WDT 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_WDT_0_INT, qm_wdt_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_wdt_0_isr);
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/**
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* ISR for USB 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_irq_request(QM_IRQ_USB_0_INT, qm_usb_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE(qm_usb_0_isr);
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/**
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* @}
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*/
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#endif /* __QM_ISR_H__ */
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