203 lines
6.1 KiB
C
203 lines
6.1 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __QM_AON_COUNTERS_H__
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#define __QM_AON_COUNTERS_H__
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#include "qm_common.h"
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#include "qm_soc_regs.h"
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/**
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* Always-on Counters.
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*
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* @note The always on counters are in the 32kHz clock domain. Some register
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* operations take a minimum of a 32kHz clock cycle to complete.
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*
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* @defgroup groupAONC Always-on Counters
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* @{
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*/
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/**
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* Always on counter status.
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*/
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typedef enum {
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/**
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* Default Timer Status
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*/
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QM_AONPT_READY = 0,
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/**
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* Timer expired. Status must be cleared with qm_aonpt_clear().
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*/
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QM_AONPT_EXPIRED,
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#if (HAS_AONPT_BUSY_BIT)
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/**
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* Timer is busy. Status after an alarm clear or timer reset has
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* been initiated. Status must change back to ready before any further
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* timer configuration to prevent timer lockup.
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* This is due to the always on counter being in the 32kHz clock
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* domain.
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*/
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QM_AONPT_BUSY,
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#endif
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} qm_aonpt_status_t;
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/**
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* QM Always-on Periodic Timer configuration type.
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*/
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typedef struct {
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uint32_t count; /**< Time to count down from in clock cycles.*/
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bool int_en; /**< Enable/disable the interrupts. */
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/**
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* User callback.
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*
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* @param[in] data User defined data.
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*/
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void (*callback)(void *data);
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void *callback_data; /**< Callback data. */
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} qm_aonpt_config_t;
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/**
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* Enable the Always-on Counter.
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*
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* @param[in] aonc Always-on counter to read.
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*
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* @return Standard errno return type for QMSI.
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* @retval 0 on success.
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* @retval Negative @ref errno for possible error codes.
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*/
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int qm_aonc_enable(const qm_aonc_t aonc);
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/**
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* Disable the Always-on Counter.
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*
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* @param[in] aonc Always-on counter to read.
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*
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* @return Standard errno return type for QMSI.
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* @retval 0 on success.
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* @retval Negative @ref errno for possible error codes.
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*/
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int qm_aonc_disable(const qm_aonc_t aonc);
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/**
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* Get the current value of the Always-on Counter.
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*
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* Returns a 32-bit value which represents the number of clock cycles
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* since the counter was first enabled.
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*
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* @param[in] aonc Always-on counter to read.
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* @param[out] val Value of the counter. This must not be NULL.
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*
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* @return Standard errno return type for QMSI.
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* @retval 0 on success.
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* @retval Negative @ref errno for possible error codes.
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*/
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int qm_aonc_get_value(const qm_aonc_t aonc, uint32_t *const val);
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/**
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* Set the Always-on Periodic Timer configuration.
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*
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* This includes the initial value of the Always-on Periodic Timer,
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* the interrupt enable and the callback function that will be run
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* when the timer expiers and an interrupt is triggered.
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* The Periodic Timer is disabled if the counter is set to 0.
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*
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* @param[in] aonc Always-on counter to read.
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* @param[in] cfg New configuration for the Always-on Periodic Timer.
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* This must not be NULL.
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*
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* @return Standard errno return type for QMSI.
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* @retval 0 on success.
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* @retval Negative @ref errno for possible error codes.
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*/
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int qm_aonpt_set_config(const qm_aonc_t aonc,
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const qm_aonpt_config_t *const cfg);
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/**
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* Get the current value of the Always-on Periodic Timer.
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*
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* Returns a 32-bit value which represents the number of clock cycles
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* remaining before the timer fires.
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* This is the initial configured number minus the number of cycles that have
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* passed.
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*
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* @param[in] aonc Always-on counter to read.
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* @param[out] val Value of the Always-on Periodic Timer.
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* This must not be NULL.
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*
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* @return Standard errno return type for QMSI.
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* @retval 0 on success.
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* @retval Negative @ref errno for possible error codes.
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*/
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int qm_aonpt_get_value(const qm_aonc_t aonc, uint32_t *const val);
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/**
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* Get the current status of an Always-on Periodic Timer.
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*
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* @param[in] aonc Always-on counter to read.
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* @param[out] status Status of the Always-on Periodic Timer.
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* This must not be NULL.
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*
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* @return Standard errno return type for QMSI.
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* @retval 0 on success.
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* @retval Negative @ref errno for possible error codes.
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*/
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int qm_aonpt_get_status(const qm_aonc_t aonc, qm_aonpt_status_t *const status);
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/**
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* Clear the status of the Always-on Periodic Timer.
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*
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* The status must be clear before the Always-on Periodic Timer can trigger
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* another interrupt.
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*
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* @param[in] aonc Always-on counter to read.
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*
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* @return Standard errno return type for QMSI.
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* @retval 0 on success.
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* @retval Negative @ref errno for possible error codes.
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*/
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int qm_aonpt_clear(const qm_aonc_t aonc);
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/**
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* Reset the Always-on Periodic Timer back to the configured value.
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*
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* @param[in] aonc Always-on counter to read.
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*
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* @return Standard errno return type for QMSI.
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* @retval 0 on success.
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* @retval Negative @ref errno for possible error codes.
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*/
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int qm_aonpt_reset(const qm_aonc_t aonc);
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/**
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* @}
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*/
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#endif /* __QM_AON_COUNTERS_H__ */
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