356 lines
10 KiB
C
356 lines
10 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qm_flash.h"
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#ifndef UNIT_TEST
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#if (QUARK_SE)
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qm_flash_reg_t *qm_flash[QM_FLASH_NUM] = {(qm_flash_reg_t *)QM_FLASH_BASE_0,
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(qm_flash_reg_t *)QM_FLASH_BASE_1};
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#elif(QUARK_D2000)
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qm_flash_reg_t *qm_flash[QM_FLASH_NUM] = {(qm_flash_reg_t *)QM_FLASH_BASE_0};
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#endif
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#endif
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int qm_flash_set_config(const qm_flash_t flash, const qm_flash_config_t *cfg)
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{
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QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
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QM_CHECK(cfg != NULL, -EINVAL);
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QM_CHECK(cfg->wait_states <= QM_FLASH_MAX_WAIT_STATES, -EINVAL);
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QM_CHECK(cfg->us_count <= QM_FLASH_MAX_US_COUNT, -EINVAL);
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QM_CHECK(cfg->write_disable <= QM_FLASH_WRITE_DISABLE, -EINVAL);
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qm_flash_reg_t *const controller = QM_FLASH[flash];
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controller->tmg_ctrl =
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(controller->tmg_ctrl & QM_FLASH_TMG_DEF_MASK) |
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(cfg->us_count | (cfg->wait_states << QM_FLASH_WAIT_STATE_OFFSET));
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if (QM_FLASH_WRITE_DISABLE == cfg->write_disable) {
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controller->ctrl |= QM_FLASH_WRITE_DISABLE_VAL;
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} else {
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controller->ctrl &= ~QM_FLASH_WRITE_DISABLE_VAL;
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}
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return 0;
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}
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int qm_flash_word_write(const qm_flash_t flash, const qm_flash_region_t region,
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uint32_t f_addr, const uint32_t data)
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{
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QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
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QM_CHECK(region <= QM_FLASH_REGION_NUM, -EINVAL);
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QM_CHECK(f_addr < QM_FLASH_MAX_ADDR, -EINVAL);
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volatile uint32_t *p_wr_data, *p_wr_ctrl;
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qm_flash_reg_t *const controller = QM_FLASH[flash];
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/* Rom and flash write registers are laid out the same, but different */
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/* locations in memory, so point to those to have the same function to*/
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/* update page section based on main or rom. */
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switch (region) {
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case QM_FLASH_REGION_SYS:
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p_wr_data = &controller->flash_wr_data;
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p_wr_ctrl = &controller->flash_wr_ctrl;
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#if (QUARK_D2000)
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/* Main flash memory starts after flash data section. */
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f_addr += QM_FLASH_REGION_DATA_0_SIZE;
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#endif
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break;
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#if (QUARK_D2000)
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case QM_FLASH_REGION_DATA:
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p_wr_data = &controller->flash_wr_data;
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p_wr_ctrl = &controller->flash_wr_ctrl;
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break;
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#endif
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case QM_FLASH_REGION_OTP:
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p_wr_data = &controller->rom_wr_data;
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p_wr_ctrl = &controller->rom_wr_ctrl;
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break;
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default:
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return -EINVAL;
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break;
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}
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/* Update address to include the write_address offset. */
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f_addr <<= WR_ADDR_OFFSET;
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*p_wr_data = data;
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*p_wr_ctrl = f_addr |= WR_REQ;
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/* Wait for write to finish. */
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while (!(controller->flash_stts & WR_DONE))
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;
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return 0;
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}
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int qm_flash_page_write(const qm_flash_t flash, const qm_flash_region_t region,
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uint32_t page_num, const uint32_t *const data,
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uint32_t len)
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{
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QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
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QM_CHECK(region <= QM_FLASH_REGION_NUM, -EINVAL);
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QM_CHECK(page_num <= QM_FLASH_MAX_PAGE_NUM, -EINVAL);
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QM_CHECK(data != NULL, -EINVAL);
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QM_CHECK(len <= QM_FLASH_PAGE_SIZE_DWORDS, -EINVAL);
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uint32_t i;
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volatile uint32_t *p_wr_data, *p_wr_ctrl;
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qm_flash_reg_t *const controller = QM_FLASH[flash];
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/* Rom and flash write registers are laid out the same, but different */
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/* locations in memory, so point to those to have the same function to*/
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/* update page section based on main or rom. */
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switch (region) {
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case QM_FLASH_REGION_SYS:
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#if (QUARK_D2000)
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page_num += QM_FLASH_REGION_DATA_0_PAGES;
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case QM_FLASH_REGION_DATA:
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#endif
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p_wr_data = &controller->flash_wr_data;
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p_wr_ctrl = &controller->flash_wr_ctrl;
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break;
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case QM_FLASH_REGION_OTP:
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p_wr_data = &controller->rom_wr_data;
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p_wr_ctrl = &controller->rom_wr_ctrl;
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break;
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default:
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return -EINVAL;
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break;
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}
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/* Update address to include the write_address offset. */
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page_num <<= (QM_FLASH_PAGE_SIZE_BITS + WR_ADDR_OFFSET);
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/* Erase the Flash page. */
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*p_wr_ctrl = page_num | ER_REQ;
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/* Wait for the erase to complete. */
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while (!(controller->flash_stts & ER_DONE))
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;
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/* Write bytes into Flash. */
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for (i = 0; i < len; i++) {
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*p_wr_data = data[i];
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*p_wr_ctrl = page_num;
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*p_wr_ctrl |= WR_REQ;
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page_num += QM_FLASH_ADDR_INC;
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/* Wait for write to finish. */
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while (!(controller->flash_stts & WR_DONE))
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;
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}
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return 0;
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}
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int qm_flash_page_update(const qm_flash_t flash, const qm_flash_region_t region,
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uint32_t f_addr, uint32_t *const page_buffer,
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const uint32_t *const data_buffer, uint32_t len)
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{
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QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
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QM_CHECK(region <= QM_FLASH_REGION_NUM, -EINVAL);
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QM_CHECK(f_addr < QM_FLASH_MAX_ADDR, -EINVAL);
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QM_CHECK(page_buffer != NULL, -EINVAL);
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QM_CHECK(data_buffer != NULL, -EINVAL);
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QM_CHECK(len <= QM_FLASH_PAGE_SIZE_DWORDS, -EINVAL);
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uint32_t i, j;
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volatile uint32_t *p_flash = NULL, *p_wr_data, *p_wr_ctrl;
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qm_flash_reg_t *const controller = QM_FLASH[flash];
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/* Rom and flash write registers are laid out the same, but different */
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/* locations in memory, so point to those to have the same function to*/
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/* update page section based on main or rom. */
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switch (region) {
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case QM_FLASH_REGION_SYS:
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p_wr_data = &controller->flash_wr_data;
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p_wr_ctrl = &controller->flash_wr_ctrl;
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#if (QUARK_D2000)
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p_flash = (uint32_t *)(QM_FLASH_REGION_SYS_0_BASE +
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(f_addr & QM_FLASH_PAGE_MASK));
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/* Main flash memory starts after flash data section. */
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f_addr += QM_FLASH_REGION_DATA_0_SIZE;
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#elif(QUARK_SE)
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if (flash == QM_FLASH_0) {
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p_flash = (uint32_t *)(QM_FLASH_REGION_SYS_0_BASE +
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(f_addr & QM_FLASH_PAGE_MASK));
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} else {
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p_flash = (uint32_t *)(QM_FLASH_REGION_SYS_1_BASE +
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(f_addr & QM_FLASH_PAGE_MASK));
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}
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#else
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#error("Unsupported / unspecified processor type")
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#endif
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break;
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#if (QUARK_D2000)
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case QM_FLASH_REGION_DATA:
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p_wr_data = &controller->flash_wr_data;
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p_wr_ctrl = &controller->flash_wr_ctrl;
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p_flash = (uint32_t *)(QM_FLASH_REGION_DATA_0_BASE +
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(f_addr & QM_FLASH_PAGE_MASK));
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break;
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#endif
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case QM_FLASH_REGION_OTP:
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p_wr_data = &controller->rom_wr_data;
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p_wr_ctrl = &controller->rom_wr_ctrl;
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p_flash = (uint32_t *)(QM_FLASH_REGION_OTP_0_BASE +
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(f_addr & QM_FLASH_PAGE_MASK));
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break;
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default:
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return -EINVAL;
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break;
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}
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/* Copy Flash Page, with location to be modified, to SRAM */
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for (i = 0; i < QM_FLASH_PAGE_SIZE_DWORDS; i++) {
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page_buffer[i] = *p_flash;
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p_flash++;
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}
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/* Erase the Flash page */
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*p_wr_ctrl = ((f_addr & QM_FLASH_PAGE_MASK) << WR_ADDR_OFFSET) | ER_REQ;
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/* Update sram data with new data */
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j = (f_addr & QM_FLASH_ADDRESS_MASK) >> 2;
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for (i = 0; i < len; i++, j++) {
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page_buffer[j] = data_buffer[i];
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}
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/* Wait for the erase to complete */
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while (!(controller->flash_stts & ER_DONE))
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;
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/* Update address to include the write_address offset. */
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f_addr &= QM_FLASH_PAGE_MASK;
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f_addr <<= WR_ADDR_OFFSET;
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/* Copy the modified page in SRAM into Flash. */
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for (i = 0; i < QM_FLASH_PAGE_SIZE_DWORDS; i++) {
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*p_wr_data = page_buffer[i];
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*p_wr_ctrl = f_addr |= WR_REQ;
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f_addr += QM_FLASH_ADDR_INC;
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/* Wait for write to finish. */
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while (!(controller->flash_stts & WR_DONE))
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;
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}
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return 0;
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}
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int qm_flash_page_erase(const qm_flash_t flash, const qm_flash_region_t region,
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uint32_t page_num)
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{
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QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
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QM_CHECK(region <= QM_FLASH_REGION_NUM, -EINVAL);
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QM_CHECK(page_num <= QM_FLASH_MAX_PAGE_NUM, -EINVAL);
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qm_flash_reg_t *const controller = QM_FLASH[flash];
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switch (region) {
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case QM_FLASH_REGION_SYS:
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#if (QUARK_D2000)
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page_num += QM_FLASH_REGION_DATA_0_PAGES;
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case QM_FLASH_REGION_DATA:
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#endif
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controller->flash_wr_ctrl =
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(page_num << (QM_FLASH_PAGE_SIZE_BITS + WR_ADDR_OFFSET)) |
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ER_REQ;
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break;
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case QM_FLASH_REGION_OTP:
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controller->rom_wr_ctrl =
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(page_num << (QM_FLASH_PAGE_SIZE_BITS + WR_ADDR_OFFSET)) |
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ER_REQ;
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break;
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default:
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return -EINVAL;
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}
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while (!(controller->flash_stts & ER_DONE))
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;
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return 0;
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}
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int qm_flash_mass_erase(const qm_flash_t flash, const uint8_t include_rom)
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{
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QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
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qm_flash_reg_t *const controller = QM_FLASH[flash];
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/* Erase all the Flash pages */
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if (include_rom) {
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controller->ctrl |= MASS_ERASE_INFO;
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}
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controller->ctrl |= MASS_ERASE;
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while (!(controller->flash_stts & ER_DONE))
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;
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return 0;
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}
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#if (ENABLE_RESTORE_CONTEXT)
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int qm_flash_save_context(const qm_flash_t flash, qm_flash_context_t *const ctx)
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{
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QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
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QM_CHECK(ctx != NULL, -EINVAL);
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qm_flash_reg_t *const controller = QM_FLASH[flash];
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ctx->tmg_ctrl = controller->tmg_ctrl;
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ctx->ctrl = controller->ctrl;
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return 0;
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}
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int qm_flash_restore_context(const qm_flash_t flash,
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const qm_flash_context_t *const ctx)
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{
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QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
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QM_CHECK(ctx != NULL, -EINVAL);
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qm_flash_reg_t *const controller = QM_FLASH[flash];
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controller->tmg_ctrl = ctx->tmg_ctrl;
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controller->ctrl = ctx->ctrl;
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return 0;
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}
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#endif /* ENABLE_RESTORE_CONTEXT */
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