53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE.
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*/
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#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_
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#define SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_
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#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
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/* Extra state for RI5CY hardware loop registers. */
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#define SOC_ESF_MEMBERS \
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u32_t lpstart0; \
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u32_t lpend0; \
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u32_t lpcount0; \
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u32_t lpstart1; \
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u32_t lpend1; \
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u32_t lpcount1
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/* Initial saved state. */
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#define SOC_ESF_INIT \
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0xdeadbaad, \
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0xdeadbaad, \
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0xdeadbaad, \
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0xdeadbaad, \
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0xdeadbaad, \
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0xdeadbaad
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/*
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* Ensure offset macros are available in <offsets.h> for the above.
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*
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* Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR,
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* for use in assembly.
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*/
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, lpstart0); \
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GEN_OFFSET_SYM(soc_esf_t, lpend0); \
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GEN_OFFSET_SYM(soc_esf_t, lpcount0); \
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GEN_OFFSET_SYM(soc_esf_t, lpstart1); \
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GEN_OFFSET_SYM(soc_esf_t, lpend1); \
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GEN_OFFSET_SYM(soc_esf_t, lpcount1); \
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GEN_ABSOLUTE_SYM(__EVENT0_INTPTPENDCLEAR, \
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(uint32_t)&EVENT0->INTPTPENDCLEAR)
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#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
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#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_ */
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