492 lines
14 KiB
C
492 lines
14 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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* Copyright (c) 2017 RnDity Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <sys/util.h>
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#include <clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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/* Macros to fill up prescaler values */
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#define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
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#define ahb_prescaler(v) z_ahb_prescaler(v)
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#define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
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#define apb1_prescaler(v) z_apb1_prescaler(v)
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#ifndef CONFIG_SOC_SERIES_STM32F0X
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#define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
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#define apb2_prescaler(v) z_apb2_prescaler(v)
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#endif /* CONFIG_SOC_SERIES_STM32F0X */
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#define z_mco1_prescaler(v) LL_RCC_MCO1_DIV_ ## v
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#define mco1_prescaler(v) z_mco1_prescaler(v)
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#define z_mco2_prescaler(v) LL_RCC_MCO2_DIV_ ## v
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#define mco2_prescaler(v) z_mco2_prescaler(v)
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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#define __LL_RCC_CALC_HCLK_FREQ __LL_RCC_CALC_HCLK1_FREQ
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#endif /* CONFIG_SOC_SERIES_STM32F0X */
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#if CONFIG_CLOCK_STM32_AHB_PRESCALER > 1
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/*
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* AHB prescaler allows to set a HCLK frequency (feeding cortex systick)
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* lower than SYSCLK frequency (actual core frequency).
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* Though, zephyr doesn't make a difference today between these two clocks.
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* So, changing this prescaler is not allowed until it is made possible to
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* use them independently in zephyr clock subsystem.
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*/
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#error "AHB presacler can't be higher than 1"
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#endif
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/**
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* @brief fill in AHB/APB buses configuration structure
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*/
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static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
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{
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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clk_init->CPU1CLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_CPU1_PRESCALER);
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clk_init->CPU2CLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_CPU2_PRESCALER);
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clk_init->AHB4CLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_AHB4_PRESCALER);
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#else
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clk_init->AHBCLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_AHB_PRESCALER);
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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clk_init->APB1CLKDivider = apb1_prescaler(
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CONFIG_CLOCK_STM32_APB1_PRESCALER);
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
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clk_init->APB2CLKDivider = apb2_prescaler(
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CONFIG_CLOCK_STM32_APB2_PRESCALER);
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#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
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}
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static u32_t get_bus_clock(u32_t clock, u32_t prescaler)
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{
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return clock / prescaler;
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}
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static inline int stm32_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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LL_AHB1_GRP1_EnableClock(pclken->enr);
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break;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X) || \
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defined(CONFIG_SOC_SERIES_STM32F2X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_EnableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||
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CONFIG_SOC_SERIES_STM32F7X */
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_EnableClock(pclken->enr);
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break;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_EnableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_EnableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
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#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X)
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case STM32_CLOCK_BUS_IOP:
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LL_IOP_GRP1_EnableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L0X || CONFIG_SOC_SERIES_STM32G0X */
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static inline int stm32_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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LL_AHB1_GRP1_DisableClock(pclken->enr);
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break;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X) || \
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defined(CONFIG_SOC_SERIES_STM32F2X)
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_DisableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||
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CONFIG_SOC_SERIES_STM32F7X */
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_DisableClock(pclken->enr);
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break;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_DisableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_DisableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
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#ifdef CONFIG_SOC_SERIES_STM32L0X
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case STM32_CLOCK_BUS_IOP:
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LL_IOP_GRP1_DisableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L0X */
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(struct device *clock,
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clock_control_subsys_t sub_system,
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u32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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/*
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* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
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* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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* since it will be updated after clock configuration and hence
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* more likely to contain actual clock speed
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*/
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u32_t ahb_clock = SystemCoreClock;
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u32_t apb1_clock = get_bus_clock(ahb_clock,
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CONFIG_CLOCK_STM32_APB1_PRESCALER);
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
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u32_t apb2_clock = get_bus_clock(ahb_clock,
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CONFIG_CLOCK_STM32_APB2_PRESCALER);
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#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
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ARG_UNUSED(clock);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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case STM32_CLOCK_BUS_AHB2:
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#ifdef CONFIG_SOC_SERIES_STM32L0X
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case STM32_CLOCK_BUS_IOP:
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#endif /* CONFIG_SOC_SERIES_STM32L0X */
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*rate = ahb_clock;
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break;
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case STM32_CLOCK_BUS_APB1:
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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case STM32_CLOCK_BUS_APB1_2:
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#endif
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*rate = apb1_clock;
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break;
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
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case STM32_CLOCK_BUS_APB2:
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*rate = apb2_clock;
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break;
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#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static struct clock_control_driver_api stm32_clock_control_api = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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};
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/*
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* Unconditionally switch the system clock source to HSI.
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*/
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__unused
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static void stm32_clock_switch_to_hsi(u32_t ahb_prescaler)
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{
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/* Enable HSI if not enabled */
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if (LL_RCC_HSI_IsReady() != 1) {
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/* Enable HSI */
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() != 1) {
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/* Wait for HSI ready */
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}
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}
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/* Set HSI as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
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LL_RCC_SetAHBPrescaler(ahb_prescaler);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
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}
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}
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/*
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* MCO configure doesn't active requested clock source,
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* so please make sure the clock source was enabled.
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*/
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static inline void stm32_clock_control_mco_init(void)
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{
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#ifndef CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK
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LL_RCC_ConfigMCO(MCO1_SOURCE,
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mco1_prescaler(CONFIG_CLOCK_STM32_MCO1_DIV));
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#endif /* CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK */
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#ifndef CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK
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LL_RCC_ConfigMCO(MCO2_SOURCE,
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mco2_prescaler(CONFIG_CLOCK_STM32_MCO2_DIV));
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#endif /* CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK */
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}
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static int stm32_clock_control_init(struct device *dev)
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{
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LL_UTILS_ClkInitTypeDef s_ClkInitStruct;
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u32_t hclk_prescaler;
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ARG_UNUSED(dev);
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/* configure clock for AHB/APB buses */
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config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct);
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/* update local hclk prescaler variable */
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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hclk_prescaler = s_ClkInitStruct.CPU1CLKDivider;
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#else
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hclk_prescaler = s_ClkInitStruct.AHBCLKDivider;
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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/* Some clocks would be activated by default */
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config_enable_default_clocks();
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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LL_UTILS_PLLInitTypeDef s_PLLInitStruct;
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/* configure PLL input settings */
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config_pll_init(&s_PLLInitStruct);
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/*
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* Switch to HSI and disable the PLL before configuration.
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* (Switching to HSI makes sure we have a SYSCLK source in
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* case we're currently running from the PLL we're about to
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* turn off and reconfigure.)
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*
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* Don't use s_ClkInitStruct.AHBCLKDivider as the AHB
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* prescaler here. In this configuration, that's the value to
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* use when the SYSCLK source is the PLL, not HSI.
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*/
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stm32_clock_switch_to_hsi(LL_RCC_SYSCLK_DIV_1);
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LL_RCC_PLL_Disable();
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#ifdef CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ,
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
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<< RCC_PLLCFGR_PLLQ_Pos);
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#endif /* CONFIG_CLOCK_STM32_PLL_Q_DIVISOR */
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#ifdef CONFIG_CLOCK_STM32_PLL_SRC_MSI
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#ifdef CONFIG_CLOCK_STM32_MSI_PLL_MODE
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/* Enable MSI hardware auto calibration */
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LL_RCC_MSI_EnablePLLMode();
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#endif
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/* Switch to PLL with MSI as clock source */
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LL_PLL_ConfigSystemClock_MSI(&s_PLLInitStruct, &s_ClkInitStruct);
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/* Disable other clocks */
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LL_RCC_HSI_Disable();
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LL_RCC_HSE_Disable();
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#elif CONFIG_CLOCK_STM32_PLL_SRC_HSI
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/* Switch to PLL with HSI as clock source */
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LL_PLL_ConfigSystemClock_HSI(&s_PLLInitStruct, &s_ClkInitStruct);
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/* Disable other clocks */
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LL_RCC_HSE_Disable();
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LL_RCC_MSI_Disable();
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#elif CONFIG_CLOCK_STM32_PLL_SRC_HSE
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int hse_bypass = LL_UTILS_HSEBYPASS_OFF;
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#ifdef CONFIG_CLOCK_STM32_HSE_BYPASS
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hse_bypass = LL_UTILS_HSEBYPASS_ON;
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#endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */
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/* Switch to PLL with HSE as clock source */
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LL_PLL_ConfigSystemClock_HSE(
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#ifndef CONFIG_SOC_SERIES_STM32WBX
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CONFIG_CLOCK_STM32_HSE_CLOCK,
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#endif
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hse_bypass,
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&s_PLLInitStruct,
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&s_ClkInitStruct);
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/* Disable other clocks */
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LL_RCC_HSI_Disable();
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LL_RCC_MSI_Disable();
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#endif /* CONFIG_CLOCK_STM32_PLL_SRC_* */
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#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE
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/* Enable HSE if not enabled */
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if (LL_RCC_HSE_IsReady() != 1) {
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/* Check if need to enable HSE bypass feature or not */
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#ifdef CONFIG_CLOCK_STM32_HSE_BYPASS
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LL_RCC_HSE_EnableBypass();
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#else
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LL_RCC_HSE_DisableBypass();
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#endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */
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/* Enable HSE */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1) {
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/* Wait for HSE ready */
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}
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}
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/* Set HSE as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
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LL_RCC_SetAHBPrescaler(hclk_prescaler);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
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}
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/* Update SystemCoreClock variable */
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LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(
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CONFIG_CLOCK_STM32_HSE_CLOCK,
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hclk_prescaler));
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/* Set APB1 & APB2 prescaler*/
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LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
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LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
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#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
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/* Set flash latency */
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/* HSI used as SYSCLK, set latency to 0 */
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
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/* Disable other clocks */
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LL_RCC_HSI_Disable();
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LL_RCC_MSI_Disable();
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LL_RCC_PLL_Disable();
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#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI
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/* Set MSI Range */
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LL_RCC_MSI_EnableRangeSelection();
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LL_RCC_MSI_SetRange(CONFIG_CLOCK_STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos);
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/* Enable MSI if not enabled */
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if (LL_RCC_MSI_IsReady() != 1) {
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/* Enable MSI */
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LL_RCC_MSI_Enable();
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while (LL_RCC_MSI_IsReady() != 1) {
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/* Wait for HSI ready */
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}
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#ifdef CONFIG_CLOCK_STM32_MSI_PLL_MODE
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/* Enable MSI hardware auto calibration */
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LL_RCC_MSI_EnablePLLMode();
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#endif
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}
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/* Set MSI as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);
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LL_RCC_SetAHBPrescaler(hclk_prescaler);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) {
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}
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/* Update SystemCoreClock variable with MSI freq */
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/* MSI freq is defined from RUN range selection */
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LL_SetSystemCoreClock(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN,
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LL_RCC_MSI_GetRange()));
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/* Set APB1 & APB2 prescaler*/
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LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
|
|
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
|
|
#ifdef CONFIG_SOC_SERIES_STM32WBX
|
|
/* Set C2 AHB & AHB4 prescalers */
|
|
LL_C2_RCC_SetAHBPrescaler(s_ClkInitStruct->CPU2CLKDivider);
|
|
LL_RCC_SetAHB4Prescaler(s_ClkInitStruct->AHB4CLKDivider);
|
|
#endif /* CONFIG_SOC_SERIES_STM32WBX */
|
|
|
|
/* Set flash latency */
|
|
/* MSI used as SYSCLK (16MHz), set latency to 0 */
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
|
|
|
|
/* Disable other clocks */
|
|
LL_RCC_HSE_Disable();
|
|
LL_RCC_HSI_Disable();
|
|
LL_RCC_PLL_Disable();
|
|
|
|
#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
|
|
|
|
stm32_clock_switch_to_hsi(hclk_prescaler);
|
|
|
|
/* Update SystemCoreClock variable */
|
|
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(HSI_VALUE,
|
|
hclk_prescaler));
|
|
|
|
/* Set APB1 & APB2 prescaler*/
|
|
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
|
|
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
|
|
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
|
|
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
|
|
|
|
/* Set flash latency */
|
|
/* HSI used as SYSCLK, set latency to 0 */
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
|
|
|
|
/* Disable other clocks */
|
|
LL_RCC_HSE_Disable();
|
|
LL_RCC_MSI_Disable();
|
|
LL_RCC_PLL_Disable();
|
|
|
|
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_... */
|
|
|
|
/* configure MCO1/MCO2 based on Kconfig */
|
|
stm32_clock_control_mco_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* @brief RCC device, note that priority is intentionally set to 1 so
|
|
* that the device init runs just after SOC init
|
|
*/
|
|
DEVICE_AND_API_INIT(rcc_stm32, STM32_CLOCK_CONTROL_NAME,
|
|
&stm32_clock_control_init,
|
|
NULL, NULL,
|
|
PRE_KERNEL_1,
|
|
CONFIG_CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY,
|
|
&stm32_clock_control_api);
|