52 lines
1.4 KiB
Plaintext
52 lines
1.4 KiB
Plaintext
# Kconfig - STM32F1 PLL configuration options
|
|
#
|
|
# Copyright (c) 2019 Linaro
|
|
#
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
#
|
|
|
|
if SOC_SERIES_STM32F1X
|
|
|
|
config CLOCK_STM32_PLL_XTPRE
|
|
bool "HSE to PLL /2 prescaler"
|
|
depends on SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_PLL_SRC_HSE
|
|
help
|
|
Enable this option to enable /2 prescaler on HSE to PLL clock signal
|
|
|
|
config CLOCK_STM32_PLL_MULTIPLIER
|
|
int "PLL multiplier"
|
|
depends on CLOCK_STM32_SYSCLK_SRC_PLL
|
|
default 9
|
|
range 2 16 if SOC_STM32F10X_DENSITY_DEVICE
|
|
range 4 9 if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
|
|
help
|
|
PLL multiplier, PLL output must not exceed 72MHz. Allowed values:
|
|
Density devices: 2-16
|
|
Connectivity devices: 4 - 9 and 13 ( used for multiplication factor 6.5).
|
|
|
|
config CLOCK_STM32_PLL_PREDIV1
|
|
int "PREDIV1 Prescaler"
|
|
depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL
|
|
default 1
|
|
range 1 16
|
|
help
|
|
PREDIV1 is PLL clock signal prescaler, allowed values: 1 - 16.
|
|
|
|
config CLOCK_STM32_PLL2_MULTIPLIER
|
|
int "PLL2 multiplier"
|
|
depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_PLL_SRC_PLL2
|
|
default 8
|
|
range 8 20
|
|
help
|
|
PLL2 multiplier, allowed values: 8 - 20. 15-17-18-19 reserved
|
|
|
|
config CLOCK_STM32_PLL2_PREDIV2
|
|
int "PREDIV2 Prescaler"
|
|
depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_PLL_SRC_PLL2
|
|
default 1
|
|
range 1 16
|
|
help
|
|
PREDIV2 is PLL2 prescaler, allowed values: 1 - 16.
|
|
|
|
endif # SOC_SERIES_STM32F1X
|