142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/* pinmux_dev_quark_mcu.c - general pinmux operation */
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/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <nanokernel.h>
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#include <board.h>
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#include <device.h>
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#include <init.h>
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#include <pinmux.h>
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#include <sys_io.h>
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#include "pinmux/pinmux.h"
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#include "pinmux_quark_mcu.h"
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#define MASK_2_BITS 0x3
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static int pinmux_dev_set(struct device *dev, uint32_t pin, uint32_t func)
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{
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const struct pinmux_config *pmux = dev->config->config_info;
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/*
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* the registers are 32-bit wide, but each pin requires 2 bits
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* to set the mode (A, B, C, or D). As such we only get 16
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* pins per register... hence the math for the register mask.
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*/
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uint32_t register_offset = (pin >> 4);
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/*
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* Now figure out what is the full address for the register
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* we are looking for. Add the base register to the register_mask
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*/
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volatile uint32_t *mux_register =
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(uint32_t *)PINMUX_SELECT_REGISTER(pmux->base_address,
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register_offset);
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/*
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* Finally grab the pin offset within the register
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*/
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uint32_t pin_no = pin % 16;
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/*
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* The value 3 is used because that is 2-bits for the mode of each
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* pin. The value 2 repesents the bits needed for each pin's mode.
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*/
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uint32_t pin_mask = MASK_2_BITS << (pin_no << 1);
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uint32_t mode_mask = func << (pin_no << 1);
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(*(mux_register)) = ((*(mux_register)) & ~pin_mask) | mode_mask;
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return 0;
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}
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static int pinmux_dev_get(struct device *dev, uint32_t pin, uint32_t *func)
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{
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const struct pinmux_config *pmux = dev->config->config_info;
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/*
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* the registers are 32-bit wide, but each pin requires 2 bits
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* to set the mode (A, B, C, or D). As such we only get 16
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* pins per register... hence the math for the register mask.
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*/
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uint32_t register_offset = pin >> 4;
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/*
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* Now figure out what is the full address for the register
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* we are looking for. Add the base register to the register_mask
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*/
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volatile uint32_t *mux_register =
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(uint32_t *)PINMUX_SELECT_REGISTER(pmux->base_address,
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register_offset);
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/*
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* Finally grab the pin offset within the register
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*/
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uint32_t pin_no = pin % 16;
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/*
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* The value 3 is used because that is 2-bits for the mode of each
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* pin. The value 2 repesents the bits needed for each pin's mode.
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*/
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uint32_t pin_mask = MASK_2_BITS << (pin_no << 1);
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uint32_t mode_mask = (*(mux_register)) & pin_mask;
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uint32_t mode = mode_mask >> (pin_no << 1);
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*func = mode;
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return 0;
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}
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static int pinmux_dev_pullup(struct device *dev,
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uint32_t pin,
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uint8_t func)
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{
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const struct pinmux_config *pmux = dev->config->config_info;
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_quark_mcu_set_mux(pmux->base_address + PINMUX_PULLUP_OFFSET,
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pin, func);
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return 0;
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}
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static int pinmux_dev_input(struct device *dev,
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uint32_t pin, uint8_t func)
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{
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const struct pinmux_config *pmux = dev->config->config_info;
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_quark_mcu_set_mux(pmux->base_address + PINMUX_INPUT_OFFSET, pin, func);
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return 0;
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}
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static struct pinmux_driver_api api_funcs = {
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.set = pinmux_dev_set,
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.get = pinmux_dev_get,
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.pullup = pinmux_dev_pullup,
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.input = pinmux_dev_input
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};
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static int pinmux_dev_initialize(struct device *port)
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{
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return 0;
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}
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static struct pinmux_config board_pmux = {
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.base_address = PINMUX_BASE_ADDR,
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};
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DEVICE_AND_API_INIT(pmux_dev, CONFIG_PINMUX_DEV_NAME,
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&pinmux_dev_initialize,
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NULL, &board_pmux,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&api_funcs);
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