zephyr/drivers/interrupt_controller
Chuck Jordan 4ad41d8d7f arc: early init should invalidate d-cache and set vector table
Some ARC targets can have a data-cache. Although there is no special
instruction to clear exceptions during early init, it is necessary to
invalidate the d-cache BEFORE any data is fetched. The ARC on arduino 101
doesn't have d-cache, and will thus skip this d-cache invalidate.

Also, it is important to set the vector table base register to point to
the interrupt vector table EARLY, so that if an exception is encountered,
the correct vector table is found. Set this base only if it is found to be
different from the one compiled in to the code.
These initialization steps assure that proper exception handling
is in place during early init.

Change-Id: Ie8b5928e5813e104680a6d6510c85d32dc8ed8f3
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-11 11:10:52 +00:00
..
Kconfig
Kconfig.stm32 stm32: rename CONFIG_SOC_STM32 -> CONFIG_SOC_FAMILY_STM32 2016-04-18 21:24:58 +00:00
Makefile stm32: rename CONFIG_SOC_STM32 -> CONFIG_SOC_FAMILY_STM32 2016-04-18 21:24:58 +00:00
arcv2_irq_unit.c arc: early init should invalidate d-cache and set vector table 2016-05-11 11:10:52 +00:00
exti_stm32.c stm32: rename SOC_STM32F1X -> SOC_SERIES_STM32F1X 2016-04-18 21:24:58 +00:00
exti_stm32.h
i8259.c
ioapic_intr.c
ioapic_priv.h
loapic_intr.c
loapic_spurious.S
mvic.c
system_apic.c