403 lines
8.9 KiB
C
403 lines
8.9 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Driver for the Atmel SAM3 PIO Controller.
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*/
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#include <errno.h>
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#include <nanokernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <gpio.h>
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#include "gpio_utils.h"
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#include "gpio_api_compat.h"
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typedef void (*config_func_t)(struct device *port);
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/* Configuration data */
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struct gpio_sam3_config {
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volatile struct __pio *port;
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/* callbacks */
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sys_slist_t cb;
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config_func_t config_func;
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};
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static void _config(struct device *dev, uint32_t mask, int flags)
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{
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struct gpio_sam3_config *cfg = dev->config->config_info;
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/* Disable the pin and return as setup is meaningless now */
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if (flags & GPIO_PIN_DISABLE) {
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cfg->port->pdr = mask;
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return;
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}
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/* Setup the pin direction */
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
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cfg->port->oer = mask;
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} else {
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cfg->port->odr = mask;
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}
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/* Setup interrupt config */
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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cfg->port->aimdr = mask;
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} else {
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cfg->port->aimer = mask;
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if (flags & GPIO_INT_EDGE) {
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cfg->port->esr = mask;
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} else if (flags & GPIO_INT_LEVEL) {
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cfg->port->lsr = mask;
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}
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if (flags & GPIO_INT_ACTIVE_LOW) {
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cfg->port->fellsr = mask;
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} else if (flags & GPIO_INT_ACTIVE_HIGH) {
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cfg->port->rehlsr = mask;
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}
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}
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}
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/* Pull-up? */
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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/* Enable pull-up */
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cfg->port->puer = mask;
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} else {
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/* Disable pull-up */
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cfg->port->pudr = mask;
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}
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/* Debounce */
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if (flags & GPIO_INT_DEBOUNCE) {
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cfg->port->difsr = mask;
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} else {
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cfg->port->scifsr = mask;
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}
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/* Enable the pin last after pin setup */
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if (flags & GPIO_PIN_ENABLE) {
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cfg->port->per = mask;
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}
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}
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/**
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* @brief Configurate pin or port
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sam3_config(struct device *dev, int access_op,
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uint32_t pin, int flags)
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{
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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_config(dev, BIT(pin), flags);
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break;
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case GPIO_ACCESS_BY_PORT:
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_config(dev, (0xFFFFFFFF), flags);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* @brief Set the pin or port output
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param value Value to set (0 or 1)
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sam3_write(struct device *dev, int access_op,
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uint32_t pin, uint32_t value)
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{
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struct gpio_sam3_config *cfg = dev->config->config_info;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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if (value) {
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/* set the pin */
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cfg->port->sodr = BIT(pin);
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} else {
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/* clear the pin */
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cfg->port->codr = BIT(pin);
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}
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break;
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case GPIO_ACCESS_BY_PORT:
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if (value) {
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/* set all pins */
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cfg->port->sodr = 0xFFFFFFFF;
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} else {
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/* clear all pins */
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cfg->port->codr = 0xFFFFFFFF;
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* @brief Read the pin or port status
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param value Value of input pin(s)
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sam3_read(struct device *dev, int access_op,
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uint32_t pin, uint32_t *value)
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{
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struct gpio_sam3_config *cfg = dev->config->config_info;
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*value = cfg->port->pdsr;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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*value = (*value >> pin) & 0x01;
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break;
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case GPIO_ACCESS_BY_PORT:
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static void gpio_sam3_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct gpio_sam3_config *cfg = dev->config->config_info;
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uint32_t int_stat;
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int_stat = cfg->port->isr;
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_gpio_fire_callbacks(&cfg->cb, dev, int_stat);
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}
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static int gpio_sam3_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_sam3_config *cfg = dev->config->config_info;
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_gpio_manage_callback(&cfg->cb, callback, set);
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return 0;
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}
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static int gpio_sam3_enable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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struct gpio_sam3_config *cfg = dev->config->config_info;
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uint32_t mask;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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mask = BIT(pin);
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break;
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case GPIO_ACCESS_BY_PORT:
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mask = 0xFFFFFFFF;
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break;
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default:
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return -ENOTSUP;
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}
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_gpio_enable_callback(dev, mask);
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cfg->port->ier |= mask;
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return 0;
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}
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static int gpio_sam3_disable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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struct gpio_sam3_config *cfg = dev->config->config_info;
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uint32_t mask;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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mask = BIT(pin);
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break;
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case GPIO_ACCESS_BY_PORT:
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mask = 0xFFFFFFFF;
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break;
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default:
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return -ENOTSUP;
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}
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_gpio_disable_callback(dev, mask);
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cfg->port->idr |= mask;
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return 0;
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}
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static struct gpio_driver_api gpio_sam3_drv_api_funcs = {
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.config = gpio_sam3_config,
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.write = gpio_sam3_write,
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.read = gpio_sam3_read,
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.manage_callback = gpio_sam3_manage_callback,
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.enable_callback = gpio_sam3_enable_callback,
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.disable_callback = gpio_sam3_disable_callback,
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};
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/**
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* @brief Initialization function of MMIO
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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int gpio_sam3_init(struct device *dev)
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{
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struct gpio_sam3_config *cfg = dev->config->config_info;
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cfg->config_func(dev);
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return 0;
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}
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/* Port A */
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#ifdef CONFIG_GPIO_ATMEL_SAM3_PORTA
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void gpio_sam3_config_a(struct device *dev);
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static struct gpio_sam3_config gpio_sam3_a_cfg = {
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.port = __PIOA,
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.config_func = gpio_sam3_config_a,
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};
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DEVICE_AND_API_INIT(gpio_sam3_a, CONFIG_GPIO_ATMEL_SAM3_PORTA_DEV_NAME,
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gpio_sam3_init, NULL, &gpio_sam3_a_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam3_drv_api_funcs);
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GPIO_SETUP_COMPAT_DEV(gpio_sam3_a);
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void gpio_sam3_config_a(struct device *dev)
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{
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/* Enable clock for PIO controller */
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__PMC->pcer0 = BIT(PID_PIOA);
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IRQ_CONNECT(IRQ_PIOA, CONFIG_GPIO_ATMEL_SAM3_PORTA_IRQ_PRI,
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gpio_sam3_isr, DEVICE_GET(gpio_sam3_a), 0);
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irq_enable(IRQ_PIOA);
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}
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#endif /* CONFIG_GPIO_ATMEL_SAM3_PORTA */
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/* Port B */
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#ifdef CONFIG_GPIO_ATMEL_SAM3_PORTB
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void gpio_sam3_config_b(struct device *dev);
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static struct gpio_sam3_config gpio_sam3_b_cfg = {
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.port = __PIOB,
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.config_func = gpio_sam3_config_b,
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};
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DEVICE_AND_API_INIT(gpio_sam3_b, CONFIG_GPIO_ATMEL_SAM3_PORTB_DEV_NAME,
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gpio_sam3_init, NULL, &gpio_sam3_b_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam3_drv_api_funcs);
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GPIO_SETUP_COMPAT_DEV(gpio_sam3_b);
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void gpio_sam3_config_b(struct device *dev)
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{
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/* Enable clock for PIO controller */
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__PMC->pcer0 = BIT(PID_PIOB);
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IRQ_CONNECT(IRQ_PIOB, CONFIG_GPIO_ATMEL_SAM3_PORTB_IRQ_PRI,
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gpio_sam3_isr, DEVICE_GET(gpio_sam3_b), 0);
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irq_enable(IRQ_PIOB);
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}
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#endif /* CONFIG_GPIO_ATMEL_SAM3_PORTB */
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/* Port C */
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#ifdef CONFIG_GPIO_ATMEL_SAM3_PORTC
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void gpio_sam3_config_c(struct device *dev);
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static struct gpio_sam3_config gpio_sam3_c_cfg = {
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.port = __PIOC,
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.config_func = gpio_sam3_config_c,
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};
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DEVICE_AND_API_INIT(gpio_sam3_c, CONFIG_GPIO_ATMEL_SAM3_PORTC_DEV_NAME,
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gpio_sam3_init, NULL, &gpio_sam3_c_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam3_drv_api_funcs);
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GPIO_SETUP_COMPAT_DEV(gpio_sam3_c);
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void gpio_sam3_config_c(struct device *dev)
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{
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/* Enable clock for PIO controller */
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__PMC->pcer0 = BIT(PID_PIOC);
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IRQ_CONNECT(IRQ_PIOC, CONFIG_GPIO_ATMEL_SAM3_PORTC_IRQ_PRI,
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gpio_sam3_isr, DEVICE_GET(gpio_sam3_c), 0);
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irq_enable(IRQ_PIOC);
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}
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#endif /* CONFIG_GPIO_ATMEL_SAM3_PORTA */
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/* Port D */
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#ifdef CONFIG_GPIO_ATMEL_SAM3_PORTD
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void gpio_sam3_config_d(struct device *dev);
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static struct gpio_sam3_config gpio_sam3_d_cfg = {
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.port = __PIOD,
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.config_func = gpio_sam3_config_d,
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};
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DEVICE_AND_API_INIT(gpio_sam3_d, CONFIG_GPIO_ATMEL_SAM3_PORTD_DEV_NAME,
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gpio_sam3_init, NULL, &gpio_sam3_d_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam3_drv_api_funcs);
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GPIO_SETUP_COMPAT_DEV(gpio_sam3_d);
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void gpio_sam3_config_d(struct device *dev)
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{
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/* Enable clock for PIO controller */
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__PMC->pcer0 = BIT(PID_PIOD);
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IRQ_CONNECT(IRQ_PIOD, CONFIG_GPIO_ATMEL_SAM3_PORTD_IRQ_PRI,
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gpio_sam3_isr, DEVICE_GET(gpio_sam3_d), 0);
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irq_enable(IRQ_PIOD);
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}
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#endif /* CONFIG_GPIO_ATMEL_SAM3_PORTD */
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