136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32H7 CM7 processor
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_system.h>
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#include <arch/cpu.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#include "stm32_hsem.h"
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#if defined(CONFIG_STM32H7_DUAL_CORE)
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static int stm32h7_m4_wakeup(const struct device *arg)
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{
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/* HW semaphore and SysCfg Clock enable */
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
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LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
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if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
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/* Cortex-M4 is waiting for end of system initialization made by
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* Cortex-M7. This initialization is now finished,
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* then Cortex-M7 takes HSEM so that CM4 can continue running.
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*/
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LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID);
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} else {
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/* CM4 is not started at boot, start it now */
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LL_RCC_ForceCM4Boot();
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}
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return 0;
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}
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#endif /* CONFIG_STM32H7_DUAL_CORE */
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32h7_init(const struct device *arg)
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{
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uint32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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SCB_EnableICache();
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#ifndef CONFIG_NOCACHE_MEMORY
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if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
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SCB_EnableDCache();
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}
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#endif /* CONFIG_NOCACHE_MEMORY */
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 64 MHz from HSI */
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SystemCoreClock = 64000000;
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/* Power Configuration */
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#if !defined(SMPS) && \
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(defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) || \
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defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) || \
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defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) || \
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defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
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defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
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defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) || \
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defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT))
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#error Unsupported configuration: Selected SoC do not support SMPS
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#endif
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#if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
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LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
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#elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
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#elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
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#elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
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#elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
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#elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
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#elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
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#elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
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LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
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#else
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LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
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#endif
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
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while (LL_PWR_IsActiveFlag_VOS() == 0) {
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}
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/* Errata ES0392 Rev 8:
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* 2.2.9: Reading from AXI SRAM may lead to data read corruption
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* Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
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* register.
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* Applicable only to RevY (REV_ID 0x1003)
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*/
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if (LL_DBGMCU_GetRevisionID() == 0x1003) {
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MODIFY_REG(GPV->AXI_TARG7_FN_MOD, 0x1, 0x1);
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}
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return 0;
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}
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SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);
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#if defined(CONFIG_STM32H7_DUAL_CORE)
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/* Unlock M4 once system configuration has been done */
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SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
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#endif /* CONFIG_STM32H7_DUAL_CORE */
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