58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_backup_sram
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#include <device.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <stm32_ll_pwr.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(stm32_backup_sram, CONFIG_SOC_LOG_LEVEL);
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struct stm32_backup_sram_config {
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struct stm32_pclken pclken;
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};
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static int stm32_backup_sram_init(const struct device *dev)
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{
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const struct stm32_backup_sram_config *config = dev->config;
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int ret;
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/* enable clock for subsystem */
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const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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ret = clock_control_on(clk, (clock_control_subsys_t *)&config->pclken);
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if (ret < 0) {
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LOG_ERR("Could not initialize backup SRAM clock (%d)", ret);
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return ret;
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}
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/* enable write access to backup domain */
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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}
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/* enable backup sram regulator (required to retain backup SRAM content
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* while in standby or VBAT modes).
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*/
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LL_PWR_EnableBkUpRegulator();
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while (!LL_PWR_IsEnabledBkUpRegulator()) {
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}
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return 0;
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}
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static const struct stm32_backup_sram_config config = {
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.pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
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.enr = DT_INST_CLOCKS_CELL(0, bits) },
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};
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DEVICE_DT_INST_DEFINE(0, stm32_backup_sram_init, NULL, NULL, &config,
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POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, NULL);
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